Chip Industry Technical Paper Roundup: June 8


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DTCO of NOR-Type IGZO FeFETs for 3D Heterogeneous AI Memories: A Read-Centric Perspective 🔗 imec, KU Leuven ZK-Flex: A Flexible and Scalable Framework for Accelerating Zero-Knowledge Proofs 🔗 KAIST Thermal- and Aging-Aware Rowhamme... » read more

Scaling Nanoribbon Transistors with Monolayer TMDs (Stanford, Chalmers, Horiba, SLAC)


Researchers from Stanford University, Chalmers University of Technology, HORIBA Scientific, and SLAC National Accelerator Laboratory have published “Scaling nanoribbon transistors with monolayer transition metal dichalcogenides”. Abstract “Nanoscale transistors demand aggressive scaling of all channel dimensions—length, width and thickness. Two-dimensional semiconductors (2DS... » read more

Chip Industry Technical Paper Roundup: Dec. 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=497 /] Find more semiconductor research papers here. » read more

Formal Verification Of Secure Automotive SW Updates (Chalmers, Volvo)


A technical paper titled "Towards a Formal Verification of Secure Vehicle Software Updates" was published by researchers at Chalmers University of Technology and Volvo. Abstract "With the rise of software-defined vehicles (SDVs), where software governs most vehicle functions alongside enhanced connectivity, the need for secure software updates has become increasingly critical. Software vuln... » read more

Chip Industry Week In Review


China's Hefei Lumiverse Technology reportedly has developed a desktop-sized High Harmonic Generation light source that generates wavelengths as small as 1nm. One customer already has used it to produce 14nm chips, which was the original target node for EUV, according to one report. As a point of comparison, TSMC and Samsung didn't start using EUV until the 7nm node, relying instead on immersion... » read more

Chip Industry Technical Paper Roundup: Nov. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=488 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review


San Francisco-based Substrate raised more than $100 million to build a vertically integrated foundry that uses particle accelerators to produce "the world's brightest beams, enabling a new method of advanced X-ray lithography." The company claims its technology is comparable to ASML's high NA EUV, and notes it can extend well beyond 2nm. ASML has not publicly commented. The Nexperia chip sho... » read more

AUTOSAR-Aligned Analysis Of 180 SoC Vulnerabilities In Auto Architecture (Chalmers, Univ. of Gothenburg)


A new technical paper titled "An AUTOSAR-Aligned Architectural Study of Vulnerabilities in Automotive SoC Software" was published by researchers at Chalmers University of Technology and University of Gothenburg. Abstract "Cooperative, Connected and Automated Mobility (CCAM) are complex cyber-physical systems (CPS) that integrate computation, communication, and control in safety-critical env... » read more

Research Bits: Sept. 30


Hybrid memory for edge training and inference Researchers from CEA-Leti, Université Grenoble Alpes, CEA-List, the French National Centre for Scientific Research (CNRS), the University of Bordeaux, Bordeaux INP, IMS France, Université Paris-Saclay, and the Center for Nanosciences and Nanotechnologies developed a hybrid memory system that combines the traits of ferroelectric capacitors (FeCAP)... » read more

Chip Industry Week In Review


GlobalFoundries plans to acquire MIPS, adding RISC-V processor IP and PPA optimization software capabilities to its foundry offerings. MIPS will continue to operate as a standalone business within GF. The deal is expected to close in the second half of 2025. The EU rolled out new general-purpose AI rules this week to limit copyright infringement, protect public safety, and require transparency... » read more

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