Design Challenges Of High-Speed Wireline Transmitters

Design tradeoffs in the choice of multiplexer architecture, equalizer design, serialization technique, and output driver.


By Samad Parekh and Noman Hai

The need for higher bandwidth networking equipment as well as connectivity in the cloud and hyperscale data centers is driving the switch technology transition from 25T (terabytes) to 50T and soon to 100T. The industry has chosen Ethernet to drive the switch market, using 112G SerDes technology today and next generation architectures being designed to operate at 224Gb/s. These data rates pose extreme challenges on the entire SerDes transceiver. This article will examine some of the challenges posed on high-speed transmitters, including the choice of multiplexer architectures, the design of equalizers, data serialization rates, selecting the appropriate output driver and ensuring signal integrity.

Serialization and multiplexing challenges

Let’s start with an introduction of the overall structure of a wireline transmitter. The transmitter (TX) takes multiple lower-rate parallel data streams, serializes them into a single higher-rate data stream, and transmits it over the channel in such a way that the data is recognizable on the other end.

Fig. 1: Block diagram of a TX.

The data first enters a series of multiplexers (MUX) where each successive stage halves the number of inputs and doubles the data rate at the output until there is one data stream. Consider the 112Gb/s case where there are 64 inputs running at 1.75Gb/s that have to be serialized. Whereas CMOS logic can be used as the first few stages, the latter stages may be CML-based (current mode logic) to accommodate the higher switching speeds to satisfy power-speed trade-off [1].

A full-rate TX architecture is shown below.

Fig. 2: A full-rate TX architecture.

The final flip-flop (FF) has stringent timing and clocking requirements. However, as we go up the chain the clock divides and timing requirements are also relaxed. In figure 2, the serialization stages are shown as five-latch 2:1 MUX and this specific MUX structure can continue up in the serializer stages. However, other MUX architectures are available including three-latch MUX, one-latch MUX, no-latch MUX, or a combination of these circuits.

Equalization techniques for high-speed transmitters

After the data is serialized, it must be equalized to compensate for the frequency-dependent loss of the communication channel. Most commonly this equalization is performed using a discrete time Feed Forward Equalizer (FFE). Discrete time FFE architectures have the benefit of low noise amplification, ability to cancel pre-cursors and to accurately control tap weights, and efficiency in terms of circuit realization on-chip. Figure 3 below shows a waveform plotted in the PrimeWave Design Environment of how an FFE can equalize a closed eye.

Fig. 3: An FFE example showing an open eye after FFE equalization simulated in PrimeSim.

The industry has over time moved to more flexible, DSP-DAC based architectures, where modulation and FFE equalization is done in the digital domain, as shown in figure 4.

Fig. 4: Analog vs. DSP based TX architecture.

The TX DAC resolution is dictated by the FFE resolution which is specified for different protocols. For Ethernet applications, the DAC resolution is about 7 bits and can be implemented as binary or thermometer coded slices, or a combination of both. The design decision is the tradeoff between linearity, output capacitance, area, and power consumption.

Data serialization rate choices: Half-rate, quarter-rate, and octal-rate

Choosing the final data serialization rate is a very important design decision as a higher rate relaxes the clocking speed requirement and reduces power consumption at the expense of higher number of clock phases and increased multiplexer output capacitance. Shown in figure 5 is a half-rate TX architecture, which removes the final flip-flop and utilizes both phases of the divided clock.

Fig. 5: A half-rate TX architecture.

However, the duty cycle of these two phases affects the quality of the final output eye. This concept of half-rate architecture can be extended to quarter or octal rate MUX. The design choice tradeoff is shown in figure 6. Based on recent research, 100Gb/s transmitters utilize quarter-rate architecture due to relaxed requirements on clocks.

Fig. 6: Data rate vs. clock frequency.

Comparing output driver options for multiplexers: Current Mode Logic vs. Source-Series Terminated

The final output from the MUX must be driven across the channel with enough swing to compensate for channel losses, all while keeping power consumption in check. There are mainly two choices for the output driver: Current Mode Logic (CML) and Voltage Mode Logic (VML), also called Source-Series Terminated (SST), which are shown in figure 7. The pros and cons of the drivers are summarized in table 1.

Fig. 7: CML and SST based drivers.

Table 1: Comparing CML vs. SST based drivers.

Optimizing signal integrity

The Pad Matching Network (PMN) is very important to the signal integrity of the output eye. Though simple T-coil and pi-coils have been used in less than 50GHz applications, for data rates higher than 100Gb/s a 9th order LC network is usually employed to isolate the driver, ESD, and output pad capacitance, as shown in figure 8. This arrangement theoretically extends the output bandwidth by a factor of 2.8x. The design needs to be optimized for bandwidth, return loss and group-delay, and often requires extensive 3D electromagnetic modeling and simulation of die and package, which is enabled using the Synopsys Custom Design Platform.

Fig. 8: Pad matching network.

Synopsys 224G & 112G Ethernet IP

As the industry’s premier provider of high-speed SerDes IP, Synopsys offers a comprehensive portfolio with leading power, performance, and area, allowing designers to meet the efficient connectivity requirements of high-performance computing SoCs. Synopsys design teams have developed various novel methods of solving the design challenges imposed by 800G/1.6T high-performance computing SoCs with 224G Ethernet PHY IP and 112G Ethernet PHY IP. Join us at ISACS 2023 where we will be presenting a half-day tutorial for more in-depth discussion on this topic.

Noman Hai is a manager for the analog design team in the IP Solutions Group at Synopsys.


[1] B. Razavi, “Breaking the Speed-Power Tradeoffs in Broadband Circuits: Reviewing design techniques for transceivers up to 56 GHz,” in IEEE Nanotechnology Magazine, vol. 16, no. 3, pp. 6-15, June 2022, doi: 10.1109/MNANO.2022.3160770.

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