Week In Review: Auto, Security, Pervasive Computing

Arm’s HW security research now live; new MIPI A-Phy v.1.1; 5G C-band spurs FAA action; multiple DDR verification.


Arm shipped a prototype CHERI-enabled Morello processor, SoC, and board, the first products coming from the security Morello research program that aims to make more secure hardware that will block certain common attacks. The first board prototypes are going to testing teams at Google, Microsoft, and other major stakeholders and partners across the industry and academia.  The UKRI (UK Research and Innovation) Digital Security by Design (DSbD) initiative will distribute the first boards. (The UKRI funded the Morello Program, which Arm is heading up.)  Arm worked with University of Cambridge to adapt its CHERI (Capability Hardware Enhanced RISC Instructions) architecture, which was developed with funding originally from DARPA and then from UKRI. SRI International and University of Cambridge both worked on the CHERI architecture and ISA — the idea behind CHERI was to create a hybrid capability architecture that codes a way to put permissions into the hardware architecture, in place of integer virtual addresses, to refer to data, code, and objects in protected ways. CHERI protects memory from some hacks. “Memory safety exploits are one of the longest standing and most challenging problems in all of software security,” said David Weston, director of enterprise and OS security, Microsoft in a press release. “Using core silicon architecture to eliminate whole classes of security issues with minimal performance impact has the opportunity to be transformative with massive positive impact, I am incredibly excited about the Morello project.” CHERI adds these architectural safety features into conventional MMU-based architectures and microarchitectures, with conventional software stacks based on virtual memory and C/C++, according to the CHERI web page. The Morello prototypes architecture is embedded into an Armv8.2-A processor, adapted from an Arm Neoverse  N1 processor. The hardware is now available for testing.

Pervasive computing, 5G
In the U.S., the major telecom carriers who purchased C-band spectrum from the FCC in 2021 for billions of dollars have been working out FAA and pilot concerns about the proximity of 5G use of C-band to airport runways. The fear is that some radar altimeters on planes — which run on an adjacent spectrum to C-band — may pick up interference when landing, especially at low-visibility. The FAA is in the process of clearing specific altimeters models and approving planes to fly, with 78 plane models having been cleared. Also FAA has put in buffer zones around airports with low visibility to take off and land.

SEMI FlexTech will fund five new R&D projects using flexible hybrid electronics (FHE) with more than $5 million. The projects will concentrate on innovations for sensors, medical devices, automotive electronics, and other consumer and industrial microelectronics products.

South Korean mobile operator KT Corporation will be using Keysight‘s 5G device test solution to verify advanced 5G new radio (NR) features in its 5G services. Keysight also worked with Qualcomm to demonstrate data throughput speeds in a 3.5 Gbps uplink of 5G new radio dual connectivity (NR-DC) with mmWave carrier aggregation. Keysight’s 5G Protocol R&D Toolset and 2D multi-probe anechoic (MPAC) over-the-air (OTA) test chamber was used with a Qualcomm’s Snapdragon X65 5G Modem-RF System.

The MIPI Alliance released the A-PHY v1.1 standard, the next version of automotive serializer-deserializer (SerDes) physical-layer interface used for ADAS and ADS (cameras and displays), monitoring systems, virtual side mirrors, infotainment, among others. The maximum available downlink data rate is now 32 Gbps (doubled from 16 Gbps) and uplink gear has a data rate of up to 200 Mbps. Developers and designers will have more flexibility in adding image sensors and displays into vehicles.

Siemens and UMC collaborated on process design kits (PDKs) for UMC’s 110nm and 180nm BCD (bipolar-CMOS-DMOS) process technology, which is used for IC designs with 100V operating voltage. The product applications are in ICs in automotive and power management. Siemens built the PDKs on its Tanner software, which includes a schematic and layout editor, circuit simulators, and the Calibre design rule checking, parasitic extraction, and physical verification.

For designers of SoCs destined for systems with multiple DDR interfaces, Cadence announced it is offering DRAM IP verification for SoCs that end up in complex memory controllers, PHYs, and devices for LPDDR5x, DDR5, HBM3, and GDDR6 protocols. Usually these SoCs are used in automotive, data center, and mobile applications. The DRAM verification tools and libraries feed into the System-Level Verification IP (System VIP) tools and libraries, which is part of Cadence’s larger flows. (System VIP was announced in Oct of 2020.) “DRAM memory verification requires unique methods to ensure that all timing, power, and throughput requirements are met in various conditions,” said Paul Cunningham, senior vice president and general manager, R&D, in the System & Verification Group at Cadence. “With the industry’s first full DRAM verification solution, we’re enabling our customers to verify their IP designs effectively and ensure their designs comply with the JEDEC standard specification as well as the memory subsystem application-specific performance metrics to provide the fastest path to IP and system verification closure.” Cadence added its TripleCheck technology to the flow, which is a verification plan linked to specifications, such as JEDEC. Micron collaborated with Cadence on the flow.

Infineon introduced a smart gate driver with SPI interface to help keep 48V battery systems dependable and protect the Li-ion batteries from positive and negative voltage. The EiceDRIVER 2ED4820-EM can be used in mild hybrid electrical vehicles, trucks, e-wheelers and battery packs for solar panels. The 2ED4820-EM is in production now.

Infineon also introduced its SEMPER Solutions Hub for its SEMPER NOR flash, which is used in safety-critical, automotive applications. The hub is a toolkit to help designers integrate the flash into systems. SEMPER NOR is ISO 26262 ASIL B-compliant, ASIL D-ready, AEC-Q100 qualified, and IEC-61508 SIL 2-ready (for industrial applications.

Read more news at Manufacturing, Test and Design, Low Power.

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