A new technical paper, “In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions,” was published by researchers at the University of California, Riverside.
Abstract
“Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge to future smart chips featuring rich functionalities and ultra performance, utilizing advanced heterogeneous integration and packaging technologies. This paper discusses emerging challenges and future research directions in developing robust electrostatic discharge protection solutions for future systems-on-integrated-chiplets.”
Find the technical paper here. March 2026.
Li, Xunyu, Runyu Miao, Zijian Yue, and Albert Wang. 2026. “In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions” Semiconductors and Heterogeneous Integration 1, no. 1: 2. https://doi.org/10.3390/shi1010002
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