Chip Industry Technical Paper Roundup: May 5


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Rethinking Compute Substrates for 3D-Stacked Near-Memory LLM Decoding: Microarchitecture-Scheduling Co-Design 🔗 Univ. of Edinburgh, Peking Univ., Cambridge, CAS, HKUST In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Direct... » read more

Rethinking ESD Protection for System-On-Integrated Chiplets (UC Riverside)


A new technical paper, "In-SoIC ESD Protection for Chiplet-Based 3D Microsystems: Future Research Directions," was published by researchers at the University of California, Riverside. Abstract "Heterogeneous integration opens a pathway to three-dimensional chiplet-based microsystem chips. Electrostatic discharge reliability is a major challenge to future smart chips featuring rich functio... » read more

In-SRAM Computing Architecture Tailored For Cryptographic Acceleration Within MCUs (UC Riverside)


A new technical paper titled "CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing" was published by researchers at University of California, Riverside. Abstract "Secure communication is a critical requirement for Internet of Things (IoT) devices, which are often based on Microcontroller Units (MCUs). Current cryptographic solutions, which rely on software librari... » read more

Security Technical Paper Roundup: Sept. 30


A number of hardware security-related technical papers were presented at the August 2025 USENIX Security Symposium. The organization provides open access research, and the presentation slides and papers are free to the public. Topics include side-channel attacks and defenses, embedded security, fuzzing, fault injection, rowhammer, and more. Here are some highlights with associated links: [ta... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Chip Industry Technical Paper Roundup: June 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=442 /] Find more semiconductor research papers here. » read more

Review Paper: Wafer-Scale Accelerators Versus GPUs (UC Riverside)


A new technical paper titled "Performance, efficiency, and cost analysis of wafer-scale AI accelerators vs. single-chip GPUs" was published by researchers at UC Riverside. "This review compares wafer-scale AI accelerators and single-chip GPUs, examining performance, energy efficiency, and cost in high-performance AI applications. It highlights enabling technologies like TSMC’s chip-on-wafe... » read more

Chip Industry Technical Paper Roundup: July 22


New technical papers recently added to Semiconductor Engineering’s library. [table id=245 /] More ReadingTechnical Paper Library home » read more

Excitonic Phenomena in TMDs (Harvard, Google, Stanford et al.)


A new technical paper titled "Dynamical Control of Excitons in Atomically Thin Semiconductors" was published by researchers at Harvard University, Google Research, Stanford University, UC Riverside and others. Abstract "Excitons in transition metal dichalcogenides (TMDs) have emerged as a promising platform for novel applications ranging from optoelectronic devices to quantum optics and sol... » read more

Chip Industry Technical Paper Roundup: April 2


New technical papers recently added to Semiconductor Engineering’s library. [table id=211 /] Find last week’s technical paper additions here. » read more

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