Chip Industry Technical Paper Roundup: April 2

AI and memory wall; interrupt-resilient HW trojans; bandwidth-effective DRAM cache for GPUs with SCM; GenAI through lens of formal verification; optimizing quantum gates for error correction; event-based NN on neuromorphic architecture; HW implementation of memristor ANNs; superconducting qubits using industry-standard semi manufacturing.


New technical papers recently added to Semiconductor Engineering’s library.

Technical Paper Research Organizations
Towards Practical Fabrication Stage Attacks Using Interrupt-Resilient Hardware Trojans Georgia Tech
Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory POSTECH and Songsil University
High-coherence superconducting qubits made using industry-standard, advanced semiconductor manufacturing imec and KU Leuven
AI and Memory Wall UC Berkeley, ICSI, and LBNL
All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification Infineon Technologies
Optimizing quantum gates towards the scale of logical qubits Google AI and UC Riverside
Optimizing event-based neural networks on digital neuromorphic architecture: a comprehensive design space exploration imec, TU Delft and University of Twente
Hardware implementation of memristor-based artificial neural networks KAUST, Universitat Autònoma de Barcelona, IBM Research, USC, University of Michigan and others

Find last week’s technical paper additions here.

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