Chip Industry Technical Paper Roundup: March 26

U.S. strategy on microelectronics; standard cell layout automation; penning micro-trap for quantum; TCAM-SSD; predicting warpage early in package design; open HW in quantum; van der Waals heterojunctions; cleaner semi manufacturing.


New technical papers recently added to Semiconductor Engineering’s library.

Technical Paper Research Organizations
National Strategy on Microelectronics Research White House Office of Science and Technology Policy (OSTP)
Novel Transformer Model Based Clustering Method for Standard Cell Design Automation Nvidia
Penning micro-trap for quantum computing ETH Zürich, Leibniz Universität Hannover, and Physikalisch-Technische Bundesanstalt
Cleaner Chips: Decarbonization in Semiconductor Manufacturing Oak Ridge National Laboratory (ORNL) / UT-Battelle
TCAM-SSD: A Framework for Search-Based Computing in Solid-State Drives University of Illinois Urbana-Champaign, Carnegie Mellon University, Samsung Electronics and Sandia National Laboratories
Warpage Study by Employing an Advanced Simulation Methodology for Assessing Chip Package Interaction Effects Siemens EDA, and Univ. Grenoble Alpes, CEA, Leti
Electrical characterization of multi-gated WSe2 /MoS2 van der Waals heterojunctions Helmholtz-Zentrum Dresden Rossendorf (HZDR), TU Dresden, National Institute for Materials Science (Japan) and NaMLab gGmbH
Open Hardware Solutions in Quantum Technology Unitary Fund, Qruise GmbH, Technical University of Valencia, Lawrence Berkeley National Laboratory, Fermi National Accelerator Laboratory, Sandia National Labs, and others

Find last week’s technical paper additions here.

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