Chip Industry Technical Paper Roundup: Feb. 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=525 /] Find more semiconductor research papers here. » read more

Automated MLIR-based HLS framework That Generates FPGA HW Designs From A Variety of CNN Layers (TU Dresden)


TU Dresden researchers published "MING: An Automated CNN-to-Edge MLIR HLS framework." Abstract "Driven by the increasing demand for low-latency and real-time processing, machine learning applications are steadily migrating toward edge computing platforms, where Field-Programmable Gate Arrays (FPGAs) are widely adopted for their energy efficiency compared to CPUs and GPUs. To generate high... » read more

Chip Industry Technical Paper Roundup: Jan 6


New technical papers recently added to Semiconductor Engineering’s library: [table id=510 /] Find more semiconductor research papers here. » read more

Exploiting Domain Wall Conduction in Nitride Ferroelectrics As A New Type of Memristive FeRAM (Kiel Univ., Fraunhofer, NaMLab, TU Dresden)


A new technical paper titled "Nitride Ferroelectric Domain Wall Memory for Next-Generation Computing" was published by researchers at Kiel University, Fraunhofer Institute for Silicon Technology (ISIT), NaMLab, and TU Dresden. Abstract "The emerging nitride ferroelectrics, such as Al1-xScxN promise to significantly advance our current information technology. In particular, two-terminal mem... » read more

The Feasibility Of Deploying FPGA-Based TCEP Synchronization In Real-World Quantum Networks


Precise time synchronization is a key challenge in building distributed quantum systems – and it plays a crucial role in secure communications, quantum computing, sensing, the foundations of future 6G networks and the quantum internet. In the paper titled "TCEP-Based Synchronization for Practical Communication Network,"researchers from TU Dresden, IIT Dharwad, Fraunhofer Institute for Inte... » read more

Chip Industry Technical Paper Roundup: Sept 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=471 /] Find more semiconductor research papers here. » read more

Heterogeneous Multi-Core Architecture Optimizing Power Consumption (TU Dresden)


A new technical paper titled "Balancing Power and Performance With Task Dependencies in Multi-Core Systems" was published by researchers at TU Dresden. Abstract "The increasing use of FPGAs necessitates energy-efficient solutions, particularly for battery-powered applications. Although power dissipation is often perceived as a hardware issue, it can be mitigated through power-saving techniq... » read more

Chip Industry Week in Review


Microsoft, OpenAI, and NVIDIA warned about power swings and physical damage to power grids increasing from AI training workloads and jointly proposed a multi-pronged approach to stabilize power in AI training data centers. Meanwhile, Anthropic issued a warning about the weaponization of agentic AI in a new 25-page Threat Intelligence report. Key concerns involve the evolution in AI-assisted ... » read more

Chip Industry Technical Paper Roundup: August 11


New technical papers recently added to Semiconductor Engineering’s library: [table id=463 /] Find more semiconductor research papers here. » read more

SpiNNaker2 Neuromorphic Platform: HW-Aware Fine-Tuning of Spiking Q-Networks (TU Dresden Et Al.)


A new technical paper titled "Hardware-Aware Fine-Tuning of Spiking Q-Networks on the SpiNNaker2 Neuromorphic Platform" was published by researchers at TU Dresden, ScaDS.AI and Centre for Tactile Internet with Human-in-the-Loop (CeTI). Excerpt "Spiking Neural Networks (SNNs) promise orders-of-magnitude lower power consumption and low-latency inference on neuromorphic hardware for a wide ran... » read more

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