Understanding Why Drain-Current in GAAFETs Deviates from Thermionic Dependence at Negative Gate Voltages (Sandia National Lab, LIST)


A new technical paper, "Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in Gate-All-Around Field Effect Transistors," was published by researchers at Sandia National Laboratories and Luxembourg Institute of Science and Technology. Abstract "Gate-All-Around Field-Effect Transistors (GAAFETs), now entering high-volume production as successors to fin field-effect tra... » read more

Chip Industry Week In Review


War impacts The Iran War's toll on the chip industry is widening. Over 95% of Taiwan's energy is imported, causing the country to secure alternative sources. Korea is also heavily dependent on energy imports from the Middle East. Shortages of key materials are cropping up everywhere. Helium from Qatar, the second largest producer behind the U.S., is constrained by hostilities in the Per... » read more

Research Bits: Mar. 17


Photonic ski jumps Researchers from Massachusetts Institute of Technology (MIT), MITRE, University of Arizona, and Sandia National Laboratories developed a new class of photonic devices that enable the precise broadcasting of light from a chip into free space. The chip uses an array of microscopic structures that curl upward, resembling tiny ski jumps, and allows control over how light is e... » read more

Chip Industry Technical Paper Roundup: Dec. 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=499 /] Find more semiconductor research papers here and in the most recent Chip Industry Week in Review.   » read more

Tunnel FETs: Surpassing the Energy Efficiency of Conventional MOSFETs (Sandia Labs)


A new technical paper titled "Next-generation tunnel FETs: exploring material perspectives and areal tunneling configurations" was published by researchers at Sandia National Laboratories. Abstract "The end of Dennard scaling, which facilitated proportional increases in computing power without added energy costs until the mid-2000s, has underscored the urgent need for innovative semicondu... » read more

Chip Industry Week in Review


SEMICON West was held in Phoenix this week, with presentations covering heterogeneous integration, AI, quantum, supply chain resilience, and more. Amid the buzz of the conference, some key manufacturing and test announcements were made this week: The strategic importance of the Phoenix area hub was highlighted. Amkor Technology broke ground this week on its advanced packaging and test camp... » read more

Non-ideal Subthreshold Swing In Aligned CNTs Due To Variable Occupancy Discrete Charge Traps (Berkeley Lab, Sandia)


A new technical paper titled "Non-ideal subthreshold swing in aligned carbon nanotube transistors due to variable occupancy discrete charge traps" was published by researchers at Lawrence Berkeley National Laboratory and Sandia National Laboratories. Excerpt "Carbon nanotube transistors have been experimentally demonstrated to reach performance comparable and even surpassing that of silicon... » read more

Chip Industry Technical Paper Roundup: August 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=460 /] Find more semiconductor research papers here. » read more

Chip Industry Week in Review


The U.S. government announced new import tariff actions and deals this week, including: The EU: 15% tariff on most goods including semiconductors. According to the EU's president, the action excludes semiconductor equipment. Copper: 50% tariff on all imports of semi-finished copper products and intensive copper derivative products, effective Aug. 1, but raw input material is excluded. ... » read more

Implications of Scalable Neuromorphic Computing (Sandia National Laboratories)


A new technical paper titled "Neuromorphic Computing: A Theoretical Framework for Time, Space, and Energy Scaling" was published by researchers at Sandia National Laboratories. Abstract "Neuromorphic computing (NMC) is increasingly viewed as a low-power alternative to conventional von Neumann architectures such as central processing units (CPUs) and graphics processing units (GPUs), however... » read more

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