Research Bits: June 8


Multi-tasking transistor Researchers at Pohang University of Science & Technology (POSTECH) developed a zinc oxide (ZnO) and tellurium (Te) heterojunction transistor technology that exhibits negative differential transconductance (NDT), where current decreases over a certain voltage range. By precisely controlling overlap length between the two materials, the team realized double negati... » read more

Chip Industry Technical Paper Roundup: Mar. 31


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations DiscoRD: An Experimental Methodology for Quickly Discovering the Reliable Read Disturbance Threshold of Real DRAM Chips 🔗 ETH Zurich, Rutgers University Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review 🔗 Univ... » read more

Research Bits: Feb. 17


Analog layout foundation model Researchers from Pohang University of Science and Technology (POSTECH) built a foundation model for automated analog circuit layout. The team used a self-supervised learning approach, in which the model learns without human-provided labels. To counter a lack of available training data, the team divided analog layouts into small patches, masked part of each lay... » read more

Research Bits: Jan. 20


ALD for Ru wiring Researchers from Ulsan National Institute of Science and Technology (UNIST), Hongik University, and Tanaka Precious Metal Technologies developed an atomic layer deposition (ALD) process for creating chip interconnects using a ruthenium (Ru) precursor with a thermal stability up to 400 °C. The high-temperature ALD process can produce dense, high-quality Ru films without deg... » read more

Chip Industry Technical Paper Roundup: Nov. 18


New technical papers recently added to Semiconductor Engineering’s library: [table id=492 /] Find more semiconductor research papers here. » read more

3D Imaging Buried Interfaces In Twisted Oxide Moirés (Cornell, SLAC, Stanford et al.)


A new technical paper titled "Mind the Gap -- Imaging Buried Interfaces in Twisted Oxide Moirés" was published by researchers at Cornell University, SLAC National Accelerator Laboratory, Stanford University, USC, North Carolina State University, University of Chicago, Institute for Basic Science and POSTECH. Abstract "The ability to tune electronic structure in twisted stacks of layered, t... » read more

Research Bits: Nov. 10


Post-doping plasma for DRAM capacitors Researchers from Ulsan National Institute of Science and Technology (UNIST), Pohang University of Science and Technology (POSTECH), and Seoul National University of Science and Technology developed a post-doping plasma (PDP) process to improve the performance of DRAM capacitors. Aluminum-doped titanium dioxide (Al-doped TiO2) is a promising material fo... » read more

Chip Industry Technical Paper Roundup: Sept 2


New technical papers recently added to Semiconductor Engineering’s library: [table id=469 /] Find more semiconductor research papers here. » read more

Chip Industry Technical Paper Roundup: August 19


New technical papers recently added to Semiconductor Engineering’s library: [table id=465 /] Find more semiconductor research papers here. » read more

In-NAND Self-Encryption Architecture In A 4D-NAND Structure (DGIST, Georgia Tech Et Al.)


A new technical paper titled "FlashVault: Versatile In-NAND Self-Encryption with Zero Area Overhead" was published by researchers at DGIST, Georgia Tech, POSTECH, Samsung Electronics, Virginia Tech, and Korea University. Abstract "We present FlashVault, an in-NAND self-encryption architecture that embeds a reconfigurable cryptographic engine into the unused silicon area of a state-of-the-ar... » read more

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