Chip Industry Technical Paper Roundup: July 1


New technical papers recently added to Semiconductor Engineering’s library: [table id=426 /] Find more semiconductor research papers here. » read more

Patterned MW-NSFETs For Sustainable Scaling (POSTECH)


A new technical paper titled "Patterned Multi-Wall Nanosheet FETs for Sustainable Scaling: Zero Gate Extension With Minimal Gate Cut Width" was published by researchers at POSTECH. Abstract "In nanosheet field-effect transistors (NSFETs), the scaling of the cell height (CH) is constrained by strict design rules related to gate extension (GE), gate cut (GC), and device-to-device distance. ... » read more

Chip Industry Technical Paper Roundup: June 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=440 /] Find more semiconductor research papers here.   » read more

Vertically Stacked ZnO/Te CFETs (POSTECH, Mokpo)


A new technical paper titled "Demonstration of Vertically Stacked ZnO/Te Complementary Field-Effect Transistor" was published by researchers at POSTECH and Mokpo National University. Abstract "The complementary field-effect transistor (CFET) structure is a highly area-efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recr... » read more

Research Bits: Apr. 15


Shape-morphing OLED panel with built-in speaker Researchers from Pohang University of Science and Technology (POSTECH) developed a flexible OLED panel that can freely transform its shape while simultaneously functioning as a speaker. The design is based on a based on a specialized ultra-thin piezoelectric polymer actuator that when integrated into a flexible OLED panel enables electrically ... » read more

Research Bits: Apr. 7


DNA scaffolds for 3D electronics Researchers from Columbia University, Brookhaven National Laboratory, and University of Minnesota used DNA to help create self-assembled 3D electronic devices with nanometer-size features. The team deposited arrays of gold squares on a surface, onto which they could attach short pieces of DNA. These served as anchors to which they could fasten eight-sided di... » read more

Chip Industry Technical Paper Roundup: Sept. 17


New technical papers recently added to Semiconductor Engineering’s library: [table id=356 /] More ReadingTechnical Paper Library home » read more

Chip Industry Week In Review


JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Chip Industry Technical Paper Roundup: April 2


New technical papers recently added to Semiconductor Engineering’s library. [table id=211 /] Find last week’s technical paper additions here. » read more

DRAM Cache for GPUs With SCM And High Bandwidth


A new technical paper titled "Bandwidth-Effective DRAM Cache for GPUs with Storage-Class Memory" was published by researchers at POSTECH and Songsil University. Abstract "We propose overcoming the memory capacity limitation of GPUs with high-capacity Storage-Class Memory (SCM) and DRAM cache. By significantly increasing the memory capacity with SCM, the GPU can capture a larger fraction o... » read more

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