tag: chip design

Advanced Design Planning In IC Compiler II
By Synopsys - 28 Feb, 2024 - Comments: 0

By Rajiv Dave, CAE Manager, Synopsys. Design exploration and planning is becoming an increasingly critical step of the design creation process as growing constraints and requirements are placed upon it. IC Compiler II has been architected from the ground up with the express focus to address the three key challenges of design planning: Capacity to handle the largest design optimally yet ... » read more

Chip Industry Silos Are Crimping Advances
By Brian Bailey - 11 Jan, 2024 - Comments: 0

Change is never easy, but it is more difficult when it involves organizational restructuring. The pace of such restructuring has been increasing over the past decade, and often it is more difficult to incorporate than technological advancements. This is due to the siloed nature of the semiconductor industry, both within the industry itself, and its relationship to surrounding industries. Inc... » read more

The Good Old Days Of EDA
By Brian Bailey - 30 Nov, 2023 - Comments: 5

Nostalgia is wonderful, but there is something about being involved in the formative years of an industry. Few people ever get to experience it, and it was probably one of the most fortuitous events to have happened in my life. Back in the early '80s, little in the way of design automation existed. There were a few gate- and transistor-level simulators, primarily for test and a few 'calculators... » read more

An Entangled Heterarchy
By Brian Bailey - 09 Nov, 2023 - Comments: 1

For decades, a form of structural hierarchy has been the principal means of handling complexity in chip design. It's not always perfect, and there is no ideal way in which to divide and conquer because that would need to focus on the analysis being performed. In fact, most systems can be viewed from a variety of different hierarchies, equally correct, and together forming a heterarchy. The e... » read more

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs (Kyungpook National University)
By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs” was published by researchers at Kyungpook National University. Abstract: "Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and sp... » read more

Unleashing The Power Of Generative AI In Chip, System, And Product Design
By Cadence - 27 Sep, 2023 - Comments: 0

The field of chip, system, and product design is a complex landscape, fraught with challenges that designers grapple with daily. The traditional design process, while robust, often falls short in addressing the increasing demands for efficiency, customization, and innovation. This white paper delves into these challenges, exploring the transformative potential of generative artificial int... » read more

Patterns And Issues In AI Chip Design
By Ed Sperling - 14 Sep, 2023 - Comments: 2

AI is becoming more than a talking point for chip and system design, taking on increasingly complex tasks that are now competitive requirements in many markets. But the inclusion of AI, along with its machine learning and deep learning subcategories, also has injected widespread confusion and uncertainty into every aspect of electronics. This is partly due to the fact that it touches so many... » read more

What Is An Integrated Circuit?
By Akanksha Soni - 10 Aug, 2023 - Comments: 0

In our modern world, just about everything is woven together by electronics. From microwaves to satellites, electronics-powered devices are infused into our every waking moment. Today, even our sleep includes digital acoustics, haptics, and analytics. But while the systems that light, connect, and move our lives can vary greatly, nearly every electronic device has one or more of the same fundam... » read more

EDA, IP Fundamentals Shift As Market Soars
By Ed Sperling - 10 Jul, 2023 - Comments: 0

EDA tools and IP continued their double-digit growth trajectory this year, despite a downturn in consumer electronics and a continued shortage of key components that took a large bite out of the semiconductor market as a whole. A just-released report from the ESD Alliance showed a 12% increase in revenue for Q1, increasing to $3.95 billion compared with $3.53 billion in the same period in 20... » read more

The Impact Of ML On Chip Design
By Ed Sperling - 22 May, 2023 - Comments: 0

Node scaling and rising complexity are increasing the time it takes to get chips out the door. At the same time, design teams are not getting larger. What is needed is a way to automate the creative process, and to not have to start every design from scratch. This is where reinforcement learning fits in, with its ability to centralize and store “tribal knowledge. Thomas Andersen, vice preside... » read more

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