Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design


Access “Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design” to explore six articles that explain how to address SoC design challenges using advanced Foundation IP solutions. Learn how these approaches enable energy efficiency, high performance, and reliability across key applications such as mobile, IoT, AI, HPC, automotive, crypto, and networking. Why read this digest... » read more

AI’s Potential And Limitations In Chip Design


Experts at the Table: Semiconductor Engineering sat down to discuss the opportunities and challenges of using AI in chip design, with Thomas Andersen, vice president for AI & Machine Learning at Synopsys; Sridhar Boinapally, senior director of analog/mixed signal tools/flow at Intel; Alex Starr, corporate fellow at AMD; Stuart Oberman, vice president for GPU hardware engineering at Nvidia; ... » read more

A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)


A new technical paper, "NL2GDS: LLM-aided interface for Open Source Chip Design," was published by researchers at University of Bristol and Rutherford Appleton Laboratory. Abstract "The growing complexity of hardware design and the widening gap between high-level specifications and register-transfer level (RTL) implementation hinder rapid prototyping and system design. We introduce NL2GDS (... » read more

Follow The AI Leader


In the 1980s, a common expression was "nobody ever got fired for buying IBM." It was considered the safe option, long after new technologies had emerged. While it may not have been the most advanced option available, it remained the safe bet. It had an established ecosystem, and it was a known quantity. But who or what is the safe bet when it comes to AI? Who has the necessary data? Who has ... » read more

Survey of GenAI Across the Full Computing Stack, From SW To Silicon (Harvard)


Harvard University researchers published "GenAI for Systems: Recurring Challenges and Design Principles from Software to Silicon." Abstract "Generative AI is reshaping how computing systems are designed, optimized, and built, yet research remains fragmented across software, architecture, and chip design communities. This paper takes a cross-stack perspective, examining how generative models... » read more

LLM-Based Learning Platform For Chip Design Education (RPTU)


RPTU University of Kaiserslautern-Landau researchers published "From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs." Abstract "This paper presents an LLM-based learning platform for chip design education, aiming to make chip design accessible to beginners without overwhelming them with technical complexity. It represents the first educational platform... » read more

Benchmark For AI-Aided Chip Design That Evaluates LLMs Across 3 Critical Tasks (UCSD, Columbia)


Researchers at UCSD and Columbia University published "ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design." Abstract "While Large Language Models (LLMs) show significant potential in hardware engineering, current benchmarks suffer from saturation and limited task diversity, failing to reflect LLMs' performance in real industrial workflows. To address t... » read more

How The EDA Industry Will Evolve In 2026


AI will continue to impact every facet of the EDA industry. Pressure will mount in 2026 on design teams to drive productivity gains while technical complexity continues to escalate. This will reshape how teams work and the tools they use. Success will be determined by balancing the trade-offs between integrated platforms and best-of-breed toolchains and developing talent internally rather than ... » read more

LLM- Based Techniques To Support Behavior-Driven Development For HW Design (U. of Bremen, DFKI)


A new technical paper titled "LLM-based Behaviour Driven Development for Hardware Design" was published by researchers at University of Bremen/DFKI. Abstract "Test and verification are essential activities in hardware and system design, but their complexity grows significantly with increasing system sizes. While Behavior Driven Development (BDD) has proven effective in software engineerin... » read more

Reducing The Expertise Required For Software Developers To Participate In Chip Creation (USC)


A new technical paper titled "A Vertically Integrated Framework for Templatized Chip Design" was published by researchers at University of Southern California. Abstract "Developers who primarily engage with software often struggle to incorporate custom hardware into their applications, even though specialized silicon can provide substantial benefits to machine learning and AI, as well as ... » read more

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