Foundation IP: Pushing the Boundaries of Energy-Efficient Chip Design

Popular Tags

Recent Comments

• David Murray on Disturbance In Verification
• Ramesh Narayanaswamy on Disturbance In Verification
• Cliff Greenberg on Research Bits: Jun. 2
• Peter Ateshian on Detect, Diagnose, And Debug Using Sensors And Functional Monitoring
• Dr. Dev Gupta on Chip Industry Week In Review
• Ed Sperling on The Sub-2nm Paradox
• Jan Hoppe on The Sub-2nm Paradox
• Jan Hoppe on Toward Agentic Verification
• Riko R on With Chiplets, What Role Does Economics Play?
• C Lytle on Flash Getting Stacked High-Bandwidth Version
• Saket Goyal on HBM Shifts Testing Left To Preserve AI Chip Yield
• Debamitro Chakraborti on Creating Agentic EDA Methodologies
• Wim Bakker on Batteries Charge To The Edge
• Ron Richter on TSV Complexity Leads To Manufacturing Bottleneck
• François on The Petabyte Problem: How AI Is Finally Making Semiconductor Manufacturing Data Actionable
• Anonymous on The One Bit Problem That Can Break a System
• JC Bouzigues - IROC Technologies on The One Bit Problem That Can Break a System
• Tom Fitzpatrick on All Software Is Hardware-Dependent
• Anonymous on Memory Wall Gets Higher
• Gregory Haley on Detecting Chemical Variability At Advanced Nodes
• Matt Groves on A Framework That Generates Chip Layouts Directly From Natural Language Specifications (U. of Bristol, RAL)
• AICHIPS on How AI Will Impact Chip Design And Designers
• Martijn Fransen on Detecting Chemical Variability At Advanced Nodes
• Narek on Digital Twins: The Cloud’s The Limit
• Freelancer on Chip Industry Talent Shortage Drives Academic Partnerships
• Chris Riches on Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
• Jon on Robust Dynamic Voltage Droop Mitigation And Power Management
• Ashfaq on Minimum Energy Per Query
• Robert Boissy on Can A Computer Science Student Be Taught To Design Hardware?
• Hank Walker on Can A Computer Science Student Be Taught To Design Hardware?
• fieke khan on Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues
• Rajiv on Chip Industry Week in Review
• Guy van der Walt - Thermco on Chiplets And 3D-ICs Add New Electrical And Mechanical Challenges
• Stephen W on Chiplet Fundamentals For Engineers: eBook
• ShrdMem256 on The Verification Conundrum
• Brendan McGuire on Wafer Probe Struggles To Adapt To Multi-Die Assemblies
• NobodyTestedThis on The Verification Conundrum
• Fiber Techs San Francisco on Agentic AI In Chip Manufacturing
• SF Fiber Techs on Oxides Bring Low Leakage Transistors To Leading-Edge Memories
• humic on Addressing Critical Tradeoffs In NPU Design
• Dr. Dev Gupta on Liquid Cooling Gains Traction In Data Centers
• Mikko Utriainen, Chipmetrics on Metrology Digs Deep To Produce Next-Generation 3D NAND
• Raymond Doerr on Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration 
• Hoyong Lee on Chiplets Vs. Soft IP: Different In Almost Every Way
• Nano Banana AI on Blog Review: Dec. 17
• JS Paek on Thermal Management In 3D-IC: Modeling Hotspots, Materials, & Cooling Strategies
• Larry K on Chiplets Vs. Soft IP: Different In Almost Every Way
• Seceon.Inc on Resilient And Optimized GenAI Systems
• Linda Christensen on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
• komputer on AI With Open And Scaled Data Sharing in IC Manufacturing (NIST)
• Sree on The Thermal Trap: How Dielectrics Limit Device Performance
• David Muncier on China GenAI: Who Will Fill The Vacuum?
• acp on Is There Still a Future for Hard Disk Drives?
• Carlos Borer on Legacy Process Nodes Going Strong
• Raj Sodhi on AI Meets Device Modeling: Transforming Compact Modeling With Machine Learning
• Jaynarayan Tudu on Semiconductor Test Faces Technology Shifts In The AI Era
• Mihai Buta on Why In-Memory Computation Is So Important For Edge AI
• Silver Luis on The Competitive Advantage Of SRAM PUF Technology
• Gretchen Patti on Advanced Packaging: A Key Technology For The Next Generation Of Electronics
• Ev roach on AI Bubble Or Boom?
• Kathleen Murphy-Weber on Chip Industry Week in Review
• Raz on Multi-Die Verification
• Paul C on Scaling Memory With Molybdenum
• JWS on Scaling Memory With Molybdenum
• Klein miller on Electrifying Everything: Power Moves Toward ICs
• Team at Rise Design Automation on What Does Semiconductor Disruption Look Like?
• masa mizuno on Physics Limits Interposer Line Lengths
• Lou Covey on What Does Semiconductor Disruption Look Like?
• Ricardo Shiroma on Complex Mix Of Processors At The Edge
• Cor on Glass Substrates Gain Momentum
• Daya Young on New Antennas And Advanced ICs Needed For 6G
• Subramanian Srikanteswara Iyer on Manufacturing At The Limits
• Doug La Tulipe on Coloring Optical Signals For More Bandwidth In Data Centers
• WH on The Hidden Cost Of Contact Resistance
• Raymond Doerr on Metrology Under Pressure: Detecting Defects in Fine-Pitch Hybrid Bonding
• Raymond Doerr on Manufacturing At The Limits
• Mallikarjun on The Evolution of DRAM
• Klein Miller on Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
• Klein Miller on Lessons From 30 Years In The Trenches On The Future Of Semiconductor Manufacturing
• Jonathan Kolber on Preparing For The Quantum Computing Age
• Pramod Gupta on Challenges In Stacking HBM
• Madeline Lueilwitz on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
• Anne Meixner on Need For KGD Drives Singulated Die Screening
• Capt kirk on Designing A Better Clock Network
• Alex Martin on AI Effort And Money Misplaced
• Hamilton Carter on AI Effort And Money Misplaced
• Ilmu Komunikasi on Reconfigurable Single-Walled CNT FeFET (Univ. of Pennsylvania, Yonsei et al.)
• Giovanni Lostumbo on Will New Processor Architectures Raise Energy Efficiency?
• Brendon Berg on ESD Guns, Transients And Testing…Oh My!
• GD on All About Interconnects
• Raimo on Crisis Ahead: Power Consumption In AI Data Centers
• Fred Chen on Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
• Fred Chen on Many Options For EUV Photoresists, No Clear Winner
• Amba Prasad on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
• Shakir Ullah on The Race To Replace Silicon
• Hwaiyu Geng, P.E. on Accelerating Semiconductor Process Development Using Virtual Design Of Experiments
• Larry Gus Christiansen on Reducing Risk In The Semiconductor Supply Chain
• Vikas Sharma on RTL Signoff vs. Functional Signoff: What’s The Difference?
• Simone on Crisis Ahead: Power Consumption In AI Data Centers
• Ron Lavallee on Can Today’s Processor Architectures Be More Efficient?
• Rashid on Can Today’s Processor Architectures Be More Efficient?
• Joseph Fjelstad on When Can I Buy A Chiplet?
• Craig Lytle on Can Today’s Processor Architectures Be More Efficient?
• Partha Thirumalai on Cognichip: Using AI To Speed Complex Chip Design
• Gopal raju on Advanced Packaging Fundamentals for Semiconductor Engineers: eBook
• Lawrence Kushner on Democratizing Design: How The CHIPS Act Is Reshaping EDA And Semiconductor Innovation
• Ken Rygler on Disruptive Changes Ahead For Photomasks?
• Jan Hoppe on Need For KGD Drives Singulated Die Screening
• B.S. DeepakSubramanyan on HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
• Dr. Subhash L. Shinde , Booz Allen, Ex. Univ. of Notre Dame, Ex. Sandia National Labs., Ex. IBM. on The Race To Glass Substrates
• Traian MUNTEAN (Honorary Professor) on A Balanced Approach To Verification
• Amba Prasad on HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
• sam on HBM Roadmap: Next-Gen High-Bandwidth Memory Architectures (KAIST’s TERALAB)
• Lentz on Agentic AI In Chip Design
• adam on RISC-V’s Increasing Influence
• Jon Taylor on RISC-V’s Increasing Influence
• Roi Mit on The DAC Valuation
• Janis Robin Schamberger on Chip Industry Week in Review
• Rashid Kukkady on New Data Center Protocols Tackle AI
• Peter Bennet on The DAC Valuation