tag: chip design

Multimodal LLM Assistant for Chip Physical Design (National Taiwan Univ., UCLA, NVIDIA)
By Technical Paper Link - 28 Oct, 2025 - Comments: 0

A new technical paper titled "Multimodal Chip Physical Design Engineer Assistant" was published by researchers at National Taiwan University, University of California, Los Angeles and NVIDIA Research. Abstract "Modern chip physical design relies heavily on Electronic Design Automation (EDA) tools, which often struggle to provide interpretable feedback or actionable guidance for improving ro... » read more

How 3D-IC Will Change Chip Design
By Ed Sperling - 08 Oct, 2025 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss 3D-IC design challenges and the impact on stacked die on EDA tools and methodologies, with John Ferguson, senior director of product management at Siemens EDA; Mick Posner, senior product group director for chiplet at IP solutions in Cadence's Compute Solutions Group; Mo Faisal of Movellus; Chris Mueth, new opportunities busine... » read more

What Does Semiconductor Disruption Look Like?
By Brian Bailey - 25 Sep, 2025 - Comments: 2

When conducting interviews for my article on the incorporation of AI within EDA tools, Anand Thiruvengadam, senior director and head of AI product management at Synopsys, said, "AI has the potential to transform how customers do chip design. The entire EDA flow can be disrupted with AI." He is not alone in making this kind of statement. Each year, I do a predictions piece, and I ask about how A... » read more

Making SoC Integration Simple – Achieve Higher Productivity and Quality
By Arteris - 27 Aug, 2025 - Comments: 0

The development of large-scale semiconductors has never been a simple task, but with the development of ever more powerful computers, software environments, and verification models, the task of designing cutting-edge chips becomes far more manageable. However, now that many chips being developed are utilizing as many as 1000 IP cores, the challenges of correctly connecting these modules togethe... » read more

Re-Architecting AI For Power
By Brian Bailey - 14 Aug, 2025 - Comments: 0

The industry is becoming increasingly concerned about the amount of power being consumed by AI, but there is no simple solution to the problem. It requires a deep understanding of the application, the software and hardware architectures at both the semiconductor and system levels, and how all of this is designed and implemented. Each piece plays a role in the total power consumed and the utilit... » read more

Agentic AI: Lots Of Little Black Boxes
By Ed Sperling - 07 Aug, 2025 - Comments: 0

AI is changing so quickly that it's not always clear how much of a security threat it poses for semiconductor design, and that uncertainty increases as AI agents are introduced into the mix. So far, the use of AI in chip design has been highly targeted. Most of what is included in design tools is some version of machine learning, bounded by tight control loops. EDA and IP vendors, large chip... » read more

Semiconductor Value Chain With A Focus On IP Providers
By Expedera - 16 Jul, 2025 - Comments: 0

By Global Semiconductor Alliance (GSA) The semiconductor industry operates within a complex and rapidly evolving ecosystem driven by continuous innovation. Central to this ecosystem is the semiconductor value chain, which includes several key stages: chip design, wafer fabrication, final assembly, and raw material sourcing. Each stage is crucial to the production and functionality of semicon... » read more

Cognichip: Using AI To Speed Complex Chip Design
By Ed Sperling And Emma Riverso - 15 Jul, 2025 - Comments: 1

AI software innovation is accelerating, while the chip design process is struggling to keep pace due to rising complexity and physical constraints. The big challenge now is how to close that gap. The solution is at least as complex as the hardware design. It requires much greater reuse of IP, along with portions of existing designs, so that not everything needs to be created from scratch. AI... » read more

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Fully Automated Hardware And Software Design Of Processor Chips (Chinese Academy Of Sciences)
By Technical Paper Link - 12 Jun, 2025 - Comments: 0

A new technical paper titled "QiMeng: Fully Automated Hardware and Software Design for Processor Chip" was published by researchers at Chinese Academy of Sciences. Abstract "Processor chip design technology serves as a key frontier driving breakthroughs in computer science and related fields. With the rapid advancement of information technology, conventional design paradigms face three majo... » read more

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