Electromagnetic Analysis and Signoff: Cost Savings

How to improve reliability, trim manufacturing costs, and shorten time to market.


By Nikolas Provatas and Magdy Abadir

We are often asked by SoC design teams about the benefits of an electromagnetic analysis and signoff methodology. Here is an overview of some of the big “cost savings”.

Time to Market Savings
Utilizing an EM crosstalk analysis and signoff methodology provides designers with an “insurance policy” against the risk of EM coupling in their SOC designs and reduces the risk of silicon re-spins. Recently, we have seen many instances of silicon failures due to EM coupling in chips that have been taped out without sufficient consideration and modeling of EM parasitics.

A silicon re-spin translates to anywhere from 3 to 6 months of delay in production release, plus of course the added manufacturing cost which can be in the order of $8M to $10M for a dedicated mask set at 7nm. The time-to-market delay translates to significant revenue losses and, possibly, loss of dominant market position due to competition serving the market first. Without the proper EM analysis tools, SoC design teams can find themselves trying to debug coupling issues “blindly” and being forced to guess on what to do, risking further delays.

With an EM crosstalk signoff methodology in place, the chances of a silicon re-spin because simulations did not match actual measurements, are significantly reduced. The tools can efficiently identify crosstalk patterns in the layout and “advise” the designers which parts of the layout should be modified, in order to improve isolation and eliminate EM coupling.

Silicon Area Savings
Designers often use white space and keep out areas to mitigate coupling with neighboring devices. Instead, using EM analysis tools to accurately model and analyze coupling interactions, a lot of the wasted space can be saved. In addition, those EM analysis tools can be used at early floor-planning stage to produce compact designs.

EM analysis tools can also enable design techniques that lead to considerable silicon area savings. For example, consider the example of a folded VCO where the capacitor bank array is folded underneath the LC coil. What’s needed is an accurate way to model the folded layout, take into account all coupling parasitics and enable designers to attempt innovative implementations and save expensive silicon area.

Power Savings
Another aspect related to EM crosstalk and the inability to accurately model it, is over-designing. In an effort to mitigate the risk of un-expected silicon failures, designers tend to use design practices that can increase the power consumption of their chips, such as the use of excessive buffering in clock networks, or the use of large amounts of decoupling caps, etc. With the right modeling of EM effects on the SoC and a complete methodology in place to highlight sources of crosstalk, the number of buffers or de-coupling capacitors can be greatly reduced, with obvious benefits in the chip’s power consumption requirements as well as area.

Helic tools such as RaptorX, Exalto and the recently introduced, Pharos, can complement the designers’ expertise with “EM Crosstalk awareness” and help them safeguard their designs from unintentional capacitive and inductive coupling.

Leave a Reply

(Note: This name will be displayed publicly)