Big Shifts In Power Electronics Packaging


The power semiconductor market is poised for remarkable growth in the next several years, fueled by the adoption of electric vehicles and renewable energy, but it also driving big changes in the packaging needed to protect and connect these devices. Packaging is playing an increasingly critical role in the transition to higher power densities, enabling more efficient power supplies, power deli... » read more

Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?


By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

Characterization, Modeling, And Model Parameter Extraction Of 5nm FinFETs


A technical paper titled “A Comprehensive RF Characterization and Modeling Methodology for the 5nm Technology Node FinFETs” was published by researchers at IIT Kanpur, MaxLinear Inc., and University of California Berkeley. Abstract: "This paper aims to provide insights into the thermal, analog, and RF attributes, as well as a novel modeling methodology, for the FinFET at the industry stan... » read more

Integration Of S-Parameters For Power Module Verification Into The Engineers’ Design Environment


By Wilfried Wessel (Siemens EDA), Simon Liebetegger (University of Applied Sciences Darmstadt), and Florian Bauer (Siemens EDA) Developing a power module requires enhanced design and verification methods. Currently, multiple iterations are needed to get the design done. Today, design and manufacturing processes are heavily dependent on physical prototypes. The reason for this is the unique s... » read more

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance


In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

Unknowns And Challenges In Advanced Packaging


Dick Otte, CEO of Promex Industries, sat down with Semiconductor Engineering to talk about unknowns in material properties, the impact on bonding, and why environmental factors are so important in complex heterogeneous packages. What follows are excerpts of that conversation. SE: Companies have been designing heterogeneous chips to take advantage of specific applications or use cases, but th... » read more

A Multi-Level Analog IC Design Flow For Fast Performance Estimation Using Template-Based Layout Generators And Structural Models


Analog IC design is a very challenging task as essential information is missing in the early design stages. Because the simulation of larger designs is exceedingly computationally expensive at lower abstraction levels, conservative assumptions are usually applied that often result in suboptimal performances such as area and power consumption. In order to enable both early performance estimates ... » read more

Signoff-Accurate Partial Layout Extraction And Early Simulation


It is a rewarding experience for EDA developers and users to collaborate on deploying advanced techniques to improve design productivity. This blog will describe the experience of collaborating with customers on a new technology for reducing the number of analog design iterations. Analog design requires that engineers balance the needs to 1) reach market quickly 2) deliver high quality 3) at lo... » read more

Parasitic Characterization Comes To Power Design Simulation


Two power design challenges are taking teams into unfamiliar territory. Wide bandgap (WBG) semiconductors target greater efficiency and density. Stricter EMI compliance regulations now come standard in mission-critical industries. Power design practices are still catching up. Simulation often takes a back seat to respinning hardware prototypes until success. What’s missing that could make sim... » read more

Dynamic in-chip current distribution simulation technology for power device layout design


Abstract: "This paper reports an in-chip current distribution verification technology for power devices that takes into account the effect of layout parasitics. The proposed method enables verification of dynamic current distribution in a chip considering the influence of layout parasitics from the initial stage of device development by brushing up each element technology of TCAD, Spice mode... » read more

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