tag: parasitics

Meeting High-Frequency And Power Density Challenges With Flip Chip MLF Packaging
By KyungSu Kim - 16 Apr, 2026 - Comments: 0

The relentless march of semiconductor scaling continues to reshape the packaging landscape, driven by Moore’s Law and the demand for higher performance in increasingly compact form factors [1]. Over the past two decades transistor density has increased exponentially, with leading-edge processes now achieving densities exceeding 100 million transistors per square millimeter. Certain applica... » read more

Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails
By Karen Chow - 26 Mar, 2026 - Comments: 0

By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

3D DRAM with CBA Technology (Georgia Tech)
By Technical Paper Link - 16 Mar, 2026 - Comments: 0

A new technical paper, "System-Technology Co-Optimization of Bitline Routing and Bonding Pathways in Monolithic 3D DRAM Architectures," was published by researchers at Georgia Tech. Abstract "3D DRAM has emerged as a promising approach for continued density scaling, but its viability is limited by routing and hybrid bonding constraints to periphery, which may degrade sensing margin, laten... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Multi-Die Assemblies Complicate Parasitic Extraction
By Ann Mutschler - 12 Jun, 2025 - Comments: 0

The shift from planar designs to multi-die assemblies with complex interconnects is transforming what had become almost an afterthought in the design process into a first-order challenge. Parasitics include things like inductance, capacitance, and resistance, which have become more problematic at advanced nodes due to increasing logic density, thinner interconnects and insulators, and a spik... » read more

Optimizing Analog With Layout In The Loop
By Benjamin Prautsch - 15 May, 2025 - Comments: 0

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

Reducing Transistor Capacitance At The 5nm Node Using A Source/Drain Contact Recess
By Pradeep Nanja - 19 Sep, 2024 - Comments: 0

In logic devices such as FinFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One potential way to reduce this parasitic capacitance is to add a source/drain contact (CT) recess step when building the source/drain metal structure. However, this additional structure can potentially increase the source/drain to via resistance. Using... » read more

Integration Hurdles For Analog And RF In Next-Gen Packages
By Gregory Haley - 23 May, 2024 - Comments: 0

A rapid increase in wireless connectivity and more sensors, coupled with a shift away from monolithic SoCs toward heterogeneous integration, is driving up the amount of analog/RF content in systems and changing the dynamics within a package. Since the early 2000s, the majority of chips used at the most advanced nodes were systems-on-chip (SoCs). All features had to fit into a single planar S... » read more

How To Get Accurate Inductance Extraction For Superconductor ICs
By Hossam Sarhan - 11 Apr, 2024 - Comments: 0

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and cloud computing requires powerful and efficient integrated circuits (ICs). More semiconductor companies are considering superconductor ICs for their unique properties that allow ultrafast processing of digital information. These properties include fa... » read more

Big Shifts In Power Electronics Packaging
By Laura Peters - 16 Nov, 2023 - Comments: 0

The power semiconductor market is poised for remarkable growth in the next several years, fueled by the adoption of electric vehicles and renewable energy, but it also driving big changes in the packaging needed to protect and connect these devices. Packaging is playing an increasingly critical role in the transition to higher power densities, enabling more efficient power supplies, power deli... » read more

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