Author's Latest Posts


Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails


By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?


By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical f... » read more

High-Performance 5G IC Designs Need High-Performance Parasitic Extraction


By Karen Chow and Salma Ahmed Elhenedy We are rapidly approaching a future where 5G telecommunications will be the norm. With its increased data speeds and bandwidth, 5G has the potential to change the way we live our lives. But what does that mean for the average person? Think about cellphones, for one. You don't just use your phone for calling or texting anymore—you surf the web, chec... » read more