High-Performance 5G IC Designs Need High-Performance Parasitic Extraction

The high frequencies and data rates involved in 5G designs makes layout verification all the more important.


By Karen Chow and Salma Ahmed Elhenedy

We are rapidly approaching a future where 5G telecommunications will be the norm. With its increased data speeds and bandwidth, 5G has the potential to change the way we live our lives. But what does that mean for the average person?

Think about cellphones, for one. You don’t just use your phone for calling or texting anymore—you surf the web, check in with social media apps, watch movies, listen to music playlists, write blogs, take and edit videos—you name it! And you do all of these things from wherever you are, not tethered to a wired network. All those different types of connection require different amounts of data, and 5G will be able to handle all of them far more quickly and efficiently.

5G provides download speeds of up to 1 Gbps, which is ten times faster than current 4G LTE networks. This speed allows businesses to quickly transfer large files, and consumers to download videos and music in a matter of seconds. In addition, 5G offers lower latency, or the time it takes for a device to receive data after sending a request. This can be beneficial for real-time applications such as gaming and virtual reality. 5G networks can handle a huge increase in traffic with minimal amounts of congestion and downtime, due in part to its flexible network architecture that makes better use of existing cellular and WiFi frequencies. For consumers, this means fewer dropped phone calls, fewer instances where videos freeze or stream slowly, and fewer delays when downloading large files.

One area where 5G will have a major impact is on the Internet of things (IoT). The IoT is a network of physical devices, vehicles, home appliances, and other items that are connected to the internet and can collect and exchange data. When your car sends you an email telling you it’s time for an oil change, or your wristband tells you to get moving, that’s the IoT at work. Of course, the IoT is also the backbone of growing infrastructures such as “smart” cities, remote medical device monitoring and operation, interconnected traffic management systems, and much, much more.

The possibilities are endless, and we are only just beginning to scratch the surface of what 5G can provide. More devices can be connected to 5G networks without impacting performance, allowing for an even wider range of applications and uses. Applications already in development include enhanced virtual reality experiences, improved data security through blockchain technology, and internet connectivity on airplanes and in rural areas, among others. Ultimately, 5G has the potential to transform our world in many ways, both large and small. 5G promises to revolutionize the way we use technology by dramatically increasing our connectivity and providing a better overall experience for both businesses and consumers.

Of course, at the heart of any electronic system are the integrated circuits (ICs) that actually execute the tasks. How does 5G affect IC design companies/semiconductor industry, why are problems hard to solve, and what does a solution need to provide to be effective?

How does 5G affect the semiconductor industry?

The advent of 5G is creating a major impact on the semiconductor companies that design and fabricate chips. Driven by the demand for faster data speeds and improved network reliability, advanced technologies such as 5G are leading to new market demands in terms of power consumption and performance levels. As a result, companies in this space must constantly upgrade their products to stay competitive. At the same time, 5G is also driving innovation in the design and manufacturing process itself. Engineers are constantly looking for ways to create smaller, faster, and more sophisticated ICs to meet the demands of 5G networks. Ultimately, these trends are putting pressure on both individual IC design firms as well as the entire semiconductor industry. But while there may be challenges ahead, there are also great opportunities for those who are prepared to embrace change and adapt to the ever-evolving landscape of modern technology.

Of course, some question whether 5G technology is actually necessary for the average consumer. Though there’s no doubt that 5G will help companies and other organizations that require a high level of network performance, does the average person need to download data at gigabit speeds or have instant access to low-latency services? However, new factors that were unforeseen several years ago are influencing the answer to that question. For example, the recent world-wide pandemic that forced many employees to work remotely instantly drove the need for faster, more reliable connectivity that could handle the huge surge in network computing now required to sustain the daily activities of businesses. People who had never downloaded a movie before were suddenly trying to download and exchange files with co-workers around the world using their home networks. And who knows what other “unpredictable” factors may emerge in the future?

5G technology is still in its early stages, and it will likely be several years before it’s fully implemented. In the meantime, while there are challenges and obstacles to overcome, it’s clear that, given the benefits it offers, 5G will be a key component of future communications strategy and technology.

5G IC design

Layout verification is a crucial step in any chip design process. This verification process ensures the physical implementation of a design meets all the physical manufacturing requirements of the foundry, commonly referred to as design rules. Layout verification is essential to optimizing the probability that the chip will meet or surpass both its yield and performance targets. By verifying a physical layout prior to sending it to production, design companies can catch any issues early on and avoid costly re-spins later on in the manufacturing process. From minimizing chip defects to reducing risks of lost revenue, layout verification is essential for ensuring a smooth and successful production cycle.

Though 5G is still in development, it’s already clear that the complexity of these chips creates significant challenges for IC designers. The high frequencies and data rates involved mean that there are many more variables to take into account, and ensuring all of these pieces work together flawlessly will be no easy task.

High frequency design

ICs are the building blocks of any electronic device, and they play a vital role in supporting 5G networks. 5G ICs must be able to handle significantly more data than their predecessors, as well as support higher frequencies. To meet these demands, 5G ICs contain a variety of operational blocks:

  • analog-to-digital converters (ADCs) convert analog signals into digital form so that they can be processed by a digital signal processor (DSP)
  • digital-to-analog converters (DACs) convert digital signals into analog form for transmission
  • phase-locked loop (PLL) circuits generate a precise clock signal for use by the DSP
  • voltage-controlled oscillators (VCOs) generate the high frequency signal that is transmitted over the air
  • low-noise amplifiers (LNAs) amplify low-level signals
  • power amplifiers (PAs) boost the power of the transmit signal so that it can reach the intended receiver

While none of these block types are new, each block type must be carefully designed to function at the high data speeds required by 5G networks. In addition, 5G ICs must be able to dissipate heat quickly to prevent damage to the circuit, and they must be highly power efficient to minimize battery drain. The successful implementation of 5G technology depends on the development of highly efficient ICs that can meet the demanding requirements of next-generation networks.

Parasitic extraction for 5G ICs

A parasitic extraction (PEX) solution for 5G ICs must be able to accurately model the high frequency signals involved in 5G networking, as well as handle the large amount of data transmitted over these networks. It must also be easy to use, so it can be incorporated into the design and verification process with minimal impact. As an example, we’ll look at how the Siemens Calibre xACT platform can be specifically tailored to the needs of IC designers working on next-generation networking technology.

The Calibre xACT platform is used to accurately and precisely extract parasitics from a variety of different circuit types, including 5G chips. More accurate PEX enables more accurate circuit simulation, resulting in a better understanding of how a 5G chip will actually function. Calibre xACT circuit simulation lets designers verify the correct operation of 5G chips before they are deployed, which is a critical element of ensuring the 5G networks will perform properly and without interruption.

Parasitic inductance

Parasitic inductance is an important performance factor at high frequencies because it influences the flow of current in a circuit. At lower frequencies, the parasitic inductance of a circuit can be safely ignored. However, at higher frequencies, parasitic inductance can reach levels that have a significant impact on the overall performance of the circuit. This is especially true for 5G chips, which operate at much higher frequencies than traditional circuits.

The Calibre xL tool accurately extracts the parasitic inductance of a circuit to enable accurate circuit simulation that makes it easier to model and simulate its performance, allowing engineers to understand and evaluate the behavior of their 5G chip design.

MIM/MOM caps

One key component used in many analog/RF design applications, including those related to 5G technology, is the capacitor. Specifically, metal-insulator-metal (MIM) and metal-oxide-metal (MOM) capacitors are popular choices among 5G IC designers due to their high-capacity density and symmetric plate design needed to meet design specifications. Thanks to these advantages, MIM/MOM capacitors can be used effectively in a variety of contexts, allowing engineers to achieve optimal performance even under demanding conditions, such as those found in a 5G network.

However, the extensive use of MIM/MOM capacitors can present a number of PEX challenges, caused by sensitivity to process variations that affect capacitive accuracy. Metal and dielectric layer thickness, for example, can have a significant impact on MIM/MOM capacitor performance. To overcome these challenges, engineers must carefully select materials and manufacturing processes that minimize process variation effects. In addition, they must design comprehensive test and characterization plans to ensure that the final circuits meet all specifications. With careful planning and execution, MIM/MOM capacitors can provide the high-performance capabilities needed for 5G designs.

The Calibre xACT 3D field solver is a valuable tool for understanding and modeling high frequency designs, including design of MIM/MOM capacitors. By accurately simulating the parasitics of these capacitors, the Calibre xACT 3D technology helps engineers ensure their 5G chip designs meet all performance requirements. With its fast field solver technology and high-accuracy calculations, the Calibre xACT 3D tool generates precise netlists that are ready for simulation.

Ease of use

The Calibre xACT platform combines Calibre xACT 3D and Calibre xL technology, using cutting-edge algorithms to calculate parasitic resistance, capacitance, and inductance within an IC layout. Whether you are dealing with a complex multi-chip design or a simple circuit, Calibre xACT 3D with Calibre xL can accurately model a layout to help designers troubleshoot any potential issues and minimize unwanted parasitics in the final product.

To enable designers to view and interact with their simulation results in a graphical environment, the Calibre Interactive interface makes it easy to quickly invoke the Calibre PEX tools to identify and troubleshoot any potential PEX issues in a design. The Calibre RVE parasitic results browser allows designers to sort capacitance values in order using any heading category, so they can more easily understand the impact of parasitics on your circuit performance. For example, designers can sort alphabetically by net name or total capacitance. In figure 1, results are sorted by the total capacitance values, so the nets with the largest Ctotal are listed at the top. The designer can then expand that net to look at individual parasitics in the layout.

Fig. 1: The Calibre RVE parasitic results browser lets designers sort results by any of the headings.

In the Calibre RVE interface, designers can also highlight components in the original layout, and highlight the net in the original schematic. Figure 2 shows a coupling capacitor highlighted.

Fig. 2: Using the Calibre RVE interface, designers can highlight selected components in both the original layout and original schematic.


The world of 5G design is a complex and ever-evolving one, with new challenges and opportunities appearing all the time. To stay ahead of the competition and create designs that can handle the high demand of a 5G network, design teams must understand the requirements of 5G IC designs and have the tools they need to effectively evaluate and troubleshoot design issues. PEX can be a significant performance factor in high-capacity, high-performance, low-power 5G IC designs. Finding and accurately resolving PEX effects in 5G IC designs is an essential component of market success. Full-featured PEX tools that provide multiple extraction technologies to accurately and precisely extract and model high-frequency designs can ensure your 5G IC designs not only get to market on time, but perform as designed for the life of the product.

Related paper:
Parasitic extraction challenges and solutions for 5G IC design

Salma Ahmed Elhenedy is a product engineer in the Calibre Design Solutions group at Siemens Digital Industries Software, focusing on parasitic extraction innovation and optimization. Elhenedy received her Bachelor of Science degree in electronics and communications engineering from Ain Shams University in Cairo.

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