Do You Really Understand The Importance Of Parasitic Extraction In Chip Designs?

Using a field solver to identify parasitic effects.


By Susanne Lachenmann and Petya Aleksandrova, Infineon Technologies, and Karen Chow, Siemens EDA

One of the biggest challenges integrated circuit (IC) designers face in today’s complex designs is effectively managing the effects of parasitic elements such as resistance, capacitance, and inductance. Parasitic elements can significantly impact chip performance of a chip, making it critical for designers to accurately model and account for these effects during the design process. Understanding the root cause of parasitic elements, how to measure their impact, and how to modify a layout to reduce their effects are all necessary components of an effective parasitic extraction (PEX) strategy. Of course, that also includes using the right tools and the right processes at the right times, as Infineon Technologies discovered during their evaluation and selection of a reference PEX tool that could provide fast, accurate results across a range of design styles and technology nodes.

Let’s take a closer look at what parasitic extraction is, why it is so important in chip design, and how it fits into the overall chip design flow. We’ll also highlight the criteria that Infineon used to select their reference field solver.

Parasitics and circuit performance

Parasitic elements are “non-ideal” unintentional circuit elements created by the physical characteristics of a circuit layout. For example, the wires that connect various components in a circuit always produce a certain amount of unintentional resistance, capacitance, and inductance. These non-ideal (parasitic) aspects of the circuit can impact the performance of the chip by introducing delays, reducing signal quality, and causing other unwanted effects.

The effects of parasitic elements are becoming increasingly significant as chip designs become more complex and feature-packed. For example, in high-speed digital circuits, delays caused by parasitic elements can impact signal integrity and reduce performance. Similarly, in analog circuits, the accuracy and stability of the circuit can be compromised by parasitic elements.

PEX is the process of extracting and modeling these unwanted effects by analyzing the circuit layout and simulating the parasitic behavior and strength of the circuit elements. With a better understanding of the behavior of their circuits, designers can refine and optimize the design layout to mitigate the impacts of the parasitic elements on circuit performance and reliability.

PEX is generally performed after the placement and routing stages for digital design, or manual layout for analog design, both of which determine the physical layout of the circuit on the chip. Designers use PEX tools to analyze the layout and feed the resulting data into a power integrity simulation tool to determine if the parasitic effects cause circuit performance to degrade so much that it no longer meets specifications. If the parasitics cause too much degradation, designers must refine the layout to reduce the parasitic values, for example by making wires wider to reduce the parasitic resistance, or by moving two sensitive lines farther apart to reduce coupling capacitance.

PEX tools

PEX tools help designers identify and rectify potential circuit performance issues early in the design and verification flow, which can save time and money down the line. By accurately modeling the parasitic behaviors of a circuit when design changes are easier to implement, designers can ensure their designs meet performance specifications and reduce the risk of costly rework.

There are two types of PEX tools—rule-based extraction tools and field solvers. A field solver uses algorithms such as finite difference method (FDM) to provide a highly accurate extraction of parasitic effects by analyzing the actual electric field in the device. Rule-based PEX tools use the results from field solvers collected over multiple designs to create a pre-defined set of rules that cover the majority of PEX conditions. Because they use this ruleset, they typically run much faster than a field solver, at the expense of some level of accuracy.


Compared to rule-based extraction tools, a field solver is much more accurate. Rule-based tools apply pre-determined rules to the design to extract parasitic effects, but these rules may not account for all the variables in the design. Because field solvers use mathematical calculations, they provide a much more accurate extraction of parasitic effects.


A field solver also offers greater flexibility in terms of design application. As designs become more complex, rule-based tools may not be equipped to handle their intricacies. A field solver can easily adapt to these complexities, as it does not rely on predetermined rules. This flexibility makes it a powerful tool across digital, analog, and mixed-signal designs.


Unlike rule-based tools, a field solver can provide full coverage of all parasitic effects. This is partly because the solver can account for certain configurations of geometries in the design that a rule-based tool may miss, but also because it can analyze all layers of the design. Rule-based tools typically only analyze certain types of structures (since that information is built into how the tool does the modeling), which may lead to inaccurate results.


While the accuracy and flexibility of field solvers are clear advantages, they come at a cost: computation time. However, recent advances in field solver technology have greatly reduced computation time, making them much more feasible for larger designs, especially when using multiple CPUs. The turnaround time of a field solver can now be brought down to a runtime similar to that of rule-based extraction tools by adding more CPUs to the PEX run.


Although field solvers may seem like a significant investment, they can actually save design companies money in the long run. By providing accurate and comprehensive parasitic extraction, field solvers can greatly reduce errors in designs and reduce the number of design iterations needed. This accuracy ultimately saves time and resources, which can lead to significant cost savings.

Infineon and PEX technology

Infineon semiconductor products are used in every conceivable market and portfolio, from the smallest mobile devices to the largest industrial applications. Supplying products that deliver their intended performance and reliability is a critical success factor, and accurate PEX is one of the essential processes in the Infineon design and verification flow.

For Infineon, selecting an efficient and accurate reference field solver is an important part of establishing a reliable PEX flow. As part of the Infineon process for benchmarking field solvers, they defined a set of acceptance criteria that includes criteria related to accuracy, as well as the ability to handle multiple technology nodes (from 130nm to 22nm) and different power technologies (including non-planar processes). Additionally, they looked for computation performance that is easily multi-threaded and adaptable to their computation infrastructure. Finally, they wanted a field solver that simplifies the generation of technology files (including those for external foundry processes) and which can be used with a large number of test structures, including process control monitoring (PCM) structures. This last requirement allows Infineon to directly correlate field solver results with physical measurement data.

After a thorough analysis of available field solver technology, Infineon selected the Calibre xACT 3D field solver from Siemens EDA as their reference field solver tool, based on their evaluation criteria and the ability of the Calibre xACT 3D tool to satisfy their most critical requirements, as described below.

Technology node coverage

Infineon was able to transfer several technology nodes in a range of 130nm to 28nm using both internal and external foundry technology runsets, as well as power technology utilizing non-planar processes. With the versatility of the Calibre xACT 3D tool, Infineon was able to keep pace with the evolving technology and remain competitive in the market.

Test structure coverage

Infineon was able to use both standard 2D/3D pattern structures and process control monitoring (PCM) structures during their evaluation of the Calibre xACT 3D tool to obtain a more complete understanding of the software’s capabilities and accuracy.

Input format coverage

The Calibre xACT 3D tool not only supports GDS input formats, but also has the capability of reading LEF/DEF format, which allows it to run on digital designs in LEF/DEF format to debug outliers and unexpected capacitance values on digital designs, giving it functionality that is quite unique among field solvers and which Infineon tested for a specific design. This flexibility was a valuable feature for Infineon, as it allowed them to work with a diverse range of inputs and design styles ranging from digital to analog to radio frequency (RF).


Infineon was able to scale the Calibre xACT 3D tool on eight CPUs with a performance greater than 2000 nets per hour. This result was a significant improvement in efficiency for Infineon and allowed them to complete more designs in a shorter amount of time.


Infineon’s evaluation of the Calibre xACT 3D tool using test patterns demonstrated the software’s ability to accurately predict capacitance values in a wide range of designs and structures. When the Calibre xACT 3D tool was run on a digital layout, 96% of the nets show less than a 5% deviation, and only ~4% had 10% deviation, further demonstrating the high accuracy of the Calibre xACT 3D field solver.


Using a field solver for parasitic extraction in chip design offers a multitude of benefits, including greater accuracy, flexibility, coverage, time-efficiency, and cost-effectiveness. While there may be an initial learning curve to using a field solver and a longer computation time, the advantages make it a powerful and valuable tool to consider. As designs become more complex, using a field solver will likely become an increasingly important aspect of chip design.

For Infineon, adopting the Calibre xACT 3D tool as their reference field solver tool played an integral role in enabling their design teams to develop accurate and efficient chip designs. The software’s versatility and capability to work with various input formats and technology nodes, as well as its performance and accuracy, made it the ideal choice for Infineon. The Calibre xACT 3D tool is a powerful solution that can help design companies achieve their goals and create innovative designs, regardless of complexity or process node.

Susanne Lachenmann is a principal engineer at Infineon Technologies. Dr. Lachenmann received a diploma in physics and a Ph.D in natural science from Eberhard-Karls University, Tübingen, Germany.

Petya Aleksandrova is a senior staff engineer, physical verification and extraction, at Infineon Technologies. Aleksandrova received a B.Sc. in electronic systems for control and management, Electronics department, Technical University of Sofia, Bulgaria, and a Ph.D. in microelectronics from the Institute of Solid State Physics, Bulgarian Academy of Sciences.

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