tag: shift left

How Far Left Can You Shift?
By Ed Sperling - 24 Jun, 2026 - Comments: 0

More steps in the design flow are shifting left, which makes a complicated design process even more complex. This includes early software prototyping, workload mapping, verification, multi-physics integration, verification, IP qualification. Frank Schirrmeister, executive director of strategic programs for System Solutions at Synopsys, talks about the increasing number of steps, the potential t... » read more

Reduce Memory Redesigns With Shift-Left
By Chun-hsiang Chang - 05 Jun, 2026 - Comments: 0

Engineering managers overseeing memory design know the pattern well: a promising architecture moves smoothly through schematic capture and into layout, only to stumble when integration testing reveals contention issues that force expensive redesigns. Address decoders that looked correct in isolation turn out to enable multiple banks simultaneously. Power switches configured for aggressive gatin... » read more

Supporting Safety Requirements from RTL Exploration Through Implementation in Semiconductor Devices (Politecnico di Torino, Synopsys)
By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "Early Functional Safety and PPA evaluation for faster digital design development," was published by researchers at Politecnico di Torino and Synopsys. Abstract "The use of semiconductor devices in safety-critical applications is increasing in both volume and complexity. Applications in markets such as automotive, data centers, and aerospace have dependability requi... » read more

Test Distribution Evolves To Meet AI Challenges
By Fabio Pizza - 12 May, 2026 - Comments: 0

The proliferation of artificial intelligence (AI) is driving rapid acceleration of the semiconductor market, which analysts now predict will reach $1 trillion this year. Many semiconductor devices will be the GPUs that populate the data centers that run AI workloads. Driven by strong, sustained investments from hyperscaler operators, high-performance computing (HPC)/AI data centers are expected... » read more

How OCP S.O.L.I.D. Completes The Data Center Security Picture
By Jasper van Woudenberg - 07 May, 2026 - Comments: 0

In 2023, the Open Compute Project launched S.A.F.E. (Security Appraisal Framework and Enablement), a standardized process for auditing data center hardware and firmware. It delivered something the industry needed: approved third-party reviewers, continuous assessments, and public reports — not just one-time certifications. S.A.F.E. provided the audit framework; what it did not provide was gui... » read more

Automated Multiphysics For Successful 3D-IC Design
By John Ferguson - 02 Apr, 2026 - Comments: 0

By John Ferguson and Sheltha Nolke For design teams adopting 3D-IC architectures, the relentless pursuit of performance and reliability brings a familiar, yet increasingly complex, set of challenges: how do we manage power, dissipate heat and navigate the intricate dance of physics within these stacked architectures? While 3D-ICs offer significant advantages in size, performance, power effic... » read more

Shift Verification Left: AI Tools For Faster, Smarter Chip Design
By Hamid Shojaei - 26 Mar, 2026 - Comments: 0

Verification activities can consume up to 70% of an overall chip project's effort, underscoring the central challenge that verification poses in today's semiconductor development (Cadence SoC Verification report). The most time-consuming activities, debugging and coverage closure, require significant coordination between design and verification teams and largely dictate overall time-to-ma... » read more

AI Energy Gap And Chiplets: Why Data Movement Matters
By Ashley Stevens - 26 Feb, 2026 - Comments: 0

At the recent Chiplet Summit 2026 preconference tutorial, the panel session, “Best Way to Make Chiplets Work,” brought together leaders from across the semiconductor ecosystem to tackle one of the most pressing challenges in advanced system design: how do we make heterogeneous, multi-die systems operate as a cohesive, energy-efficient whole for AI? While much discussion focused on st... » read more

Software-Defined Hardware-Assisted Verification: Scaling To Quadrillions Of Cycles For Verification In The AI Era
By Frank Schirrmeister - 23 Dec, 2025 - Comments: 0

The semiconductor industry is at an inflection point. The convergence of advanced multi-die architectures, AI-driven workloads, and rapidly evolving interface protocols is creating unprecedented design complexity. At the same time, market pressures demand faster time-to-market and higher performance, leaving little room for error. From data center to edge developments, users have to run softwar... » read more

Top Five Trends In RTL Signoff
By Suresh Babu Barla - 30 Oct, 2025 - Comments: 0

By Suresh Babu Barla and Rimpy Chugh The “shift left” of the development cycle is critical for the huge, complex chips used in such applications as AI and high-performance computing (HPC). Identifying design issues at the netlist stage occurs far too late in the design development process. At this point, addressing such problems demands significant effort, primarily because most design-r... » read more

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