Chip Industry Silos Are Crimping Advances

Change is never easy, but it is more difficult when it involves organizational restructuring. The pace of such restructuring has been increasing over the past decade, and often it is more difficult to incorporate than technological advancements.

This is due to the siloed nature of the semiconductor industry, both within the industry itself, and its relationship to surrounding industries. Increasingly those silos are being broken down or become friction points that inhibit optimal design. At the same time, new silos are being created.

This is a story that’s been told many times in the history of EDA, but changes are coming faster now than in the past. In the early days, logic design was independent from place-and-route, but then path delays began to dominate and closing on timing became difficult. Eventually, the two domains had to be integrated. Then power became a concern. Initially it was handled by experts, but today power has become fully integrated. Not only do new nodes bring additional issues, but application segments also bring new concerns.

Today the industry is becoming more aware about reliability, sustainability, safety, and security. Design teams no longer can say, ‘We are done,’ when a chip is released to manufacturing. In-field monitoring means a chip is always providing feedback. Systems companies now are pushing the semiconductor industry to provide what they want, rather than using what is available. Chip design is being led by an increasing number of industries, each with their own specific requirements.

Many of the required changes are structural, and many of them bring together teams that used to work alone, sometimes within a company, but increasingly within different companies and different locations.

“Within Ansys, we have been concentrating on the 3Ms,” says Marc Swinnen, director of product marketing at Ansys. “The tools the EDA industry is promoting for 3D-IC are difficult to match into the customer’s organizational structure, because they aren’t the same. They’ve got a power guy somewhere in the packaging team. They’ve got a thermal guy, they’ve got an RF guy, and they’ve got the digital guys. They have to come together and use the same tool, become part of the same team. They are not organizationally set up to do that. They would rather fit the physics to the organization than the organization to the physics.”

Within the development flow, the shift left concept is pulling domains together. “Shift left encourages overlaps of design processes that previously were sequential,” says Steve Roddy, chief marketing officer at Quadric. “Designers at all stages of product development need to pay even greater attention to what their co-workers wrestle with, both upstream and downstream. An engineer needs to be aware that specifications, algorithms, and interfaces may need to change as precursor or follow-on groups progress though their design processes.”

It also requires much better data transfer. “The challenge that slows the process down is how you exchange data between domains,” says Neil Hand, director of marketing, IC segment at Siemens EDA. “How do you make drastically different domains in the system design world understandable to each other? Over time, with domain blurring and the knowledge capture and knowledge exchange, it will fundamentally change what engineering is for the semiconductor. Part of that is breaking down the silos and encapsulating knowledge in a way that is usable by them.”

Some of these problems have existed for a long time and never been properly solved. “The old joke still applies that when you meet with the software and hardware teams at a company, they will first exchange business cards to introduce themselves,” says Frank Schirrmeister, vice president for solutions and business development at Arteris. “Similar organizational dilemmas exist for lab testing and chip verification. They have the same DNA and could benefit from coordination. And similar effects exist between RTL developers and verification engineers in their interaction with back-end digital implementation, and between chip developers and system developers worrying about effects like EM and thermal issues. I wish the industry would find a better way to cross-educate developers or find a way to frame the challenges of the different domains in constraints that help guide the respective others.”

Facing problems head-on
The adoption of 2.5D packaging techniques is forcing the semiconductor industry to face some of these problems head on. “Most companies have design groups for ASIC design, and separate internal package design groups,” says John Park, product management group director in the Custom IC & PCB Group at Cadence. “They are struggling to figure out whose job is what. Silicon stacking and 3D has blurred the line between what a package engineer is responsible for versus the die design team. More than ever, we see the two teams in a single room, planning the project from the early stages. There are many requirements for co-design between the domains of package and die.”

In this case, one company owns all the pieces. “With 3D-IC advanced packaging, everyone’s in the same box to a degree,” says Siemens’ Hand. “One is a mechanical person, but they know how to spell IC. The package designer knows how to spell IC, as well. Everyone sort of understands the baseline. It is a well-constrained, well-understood multi-physics problem, and we’re seeing progress.”

There are many open questions, however. “Chip companies treat this as a big, complicated chip, while more PCB-centric companies see them as a small but very complicated package,” says Ansys’ Swinnen. “There’s truth to both, but there are fundamental problems on both sides. The chip side is not used to dealing with more analog type routing that you need on a substrate while PCB is very familiar with this. PCB routing is river routing, while chip routing is Manhattan — very rigid, very limited in its flexibility. On the other hand, packaging tools just don’t have the capacity to handle the tens, thousands, or even millions of interconnects that are occurring on an interposer. One has capacity problem, the other has a flexibility problem.”

Many problems are being pulled into the flow earlier. “Consider IC power integrity signoff solutions,” says Rajat Chaudhry, product management group director at Cadence. “We need designers to move IR drop closure earlier in the design process at the block level. To make this happen, designers will need to bring in chip-level context to the block level so there are no major surprises at the chip-level sign-off. This could lead to significant PPA benefits, as we can sign off to lower IR drop limits and gain power savings from lower VDD. It would also improve productivity with faster IR drop closure. This design change will require EDA tools to integrate in-design analysis with very efficient automated PPA-aware fixing. EDA tools will also need to support hierarchical analysis methodologies, which can bring the chip level context to the block level earlier in the process. Hierarchical analysis will also improve productivity by enabling much better performance and capacity for final chip level signoff.”

Thermal is another area that is moving up in the flow. “Thermal is becoming part of the design process,” says Hand. “We have to do thermal, we have to do mechanically induced stress, we have to do all of the these kinds of things that were very unique, and maybe only hit the one or two super advanced cellphone manufacturers in the world. Now those technologies waterfall down to others.”

Even specialty fields like RF design now are being pulled into the mix. “Digital designers typically did not have to worry too much about electromagnetics because the frequency at which a circuit becomes inductive is around 5GHz or more,” says Swinnen. “Typically, digital signals don’t get to that frequency. Even the highest-speed microprocessors are at 4GHz. A line becomes electromagnetically active when its length is comparable to the wavelength of the signal you put on it. With an interposer, you are no longer sending them an inch or so across the chip, you’re sending them four, five, or six inches across the substrate, and often the buses are running parallel. Digital signals have become electromagnetically active. If you look at the high-speed implementation of UCIe, the maximum run length allowed is only two or three millimeters. Anything beyond that, it becomes a transmission line and none of this will work properly.”

In many cases, there is a data mobility problem. “It’s easy to get bogged down in the minutia,” says Adam Arnesen, chief systems engineer for NI’s Test & Measurement Group within Emerson. “You may be running a thermal simulation of a system during the development process. Sometime later, first silicon comes back and the validation engineer finds a problem. That person can save a lot of time if they can look back to the simulation information and see that simulation had some issues in these particular areas. Perhaps under a high thermal load on this part there were timing failures on a particular bus. The problem in a lot of the situations today is those domains don’t know how to communicate to each other. There’s information that is produced in one domain and can’t move across to the next domain. Everyone ends up re-learning the problem over and over again.”

Organizing data often means creating a model. “Doing things earlier in the design flow typically requires models of the design before implementation,” says Arteris’ Schirrmeister. “Developing models feels like being in M.C. Escher’s ‘Relativity’ staircase or his famous Penrose Triangle. It has been impossible to optimize performance, fidelity, and development cost simultaneously. Many have tried, but we never got to a feasible, cost-efficient solution that, for instance, provides fast, accurate models of processors for software development and architecture analysis. The industry sees similar effects in models that predict the effects of routing delays to optimize the interconnect using more and more metal and redistribution layers in advanced semiconductor technology. The implementation details seem too complex to be abstracted away for meaningful early analysis.”

“Digital transformations are happening across industries as companies move from manual test and data processes with disparate databases across teams to streamlined development across the enterprise,” says Niels Faché, vice president and general manager of PathWave Software Solutions at Keysight Technologies. “Connecting design and test enables sharing of data across the product lifecycle and correlating results. Even more, it allows for active feedback loops from test back into the design process, enabling fewer design cycles and faster time-to-market (digital twin). Flexible tools are needed to connect design and test systems into the greater enterprise workflows. This includes management requirements and automated test generation, compliance testing, test automation, flexible databases, data analytics, and AI optimization.”

Connecting systems
When moving to the systems level, there are additional boundaries. “When you go up to the full system level, it’s a little trickier,” says Hand. “We have the ability to do sense, compute, and actuate in a single flow for the autonomous vehicle guys. This enables trading off between those domains. What happens if my compute is a little slower? Can I trade that off with my actuators being a little bit faster? Or thanks to exponential laws in terms of real-world physics, if I can compute faster, can I use a slightly slower actuator, which might make life a whole lot simpler. This is going to be huge because systems design is where you’ve got the most freedom, where you’ve got the most ability to differentiate, where you’ve got a 10X or 100X impact on the final product.”

While the gains may be large, the obstacles are comparable. “The big problem is that we’ve all built silos around how we connect things together in automotive, or how we connect things together in aerospace, defense, or mobile,” says Mark Burton, vice chair of the Accellera Federated Simulation Standard Proposed Working Group. “There are standards to connect things together, but those standards don’t talk to each other. It is not easy to pull together system-of-system type simulations, even after decades. We still seem to be stuck in our silos, and stuck with all the problems that silos bring with them. Can we do something about that? And is it a real problem, or are people so deep in their silos that even today we don’t care enough to actually do anything about it?”

Looking at the hardware software/divide, the answer might be no. “The majority of the electronics world is highly disaggregated,” says Quadric’s Roddy. “Application developers write code for boxes that some other system company designed. The system company designed an SoC built by a distant chip vendor. And the chip vendor licensed and assembled disparate IP blocks from a variety of vendors. Bridging the gaps between all those layers of separate company boundaries requires that hardware not merely be more programmable, but also more easily programmable. Tweaking and tuning arcane microcode or writing assembly code is not the answer.”

Systems bring together many issues. “With a photonics system, you are bringing in acoustics and vibration, thermal and structural dynamics, along with the electronics,” says Chris Mueth, business development, marketing, and technical specialist at Keysight. “These people all speak different languages. There’s an interpretation required. There are barriers up and down the management chain. Management is in silos. Consider the problems with design and test. The design space is under the VP of engineering, but for the test domain, a lot of times that’s under an operational VP.”

These issues are not unique to the semiconductor industry. The quantum EDA field will have to cross barriers between physics and engineering. The two fields typically use different terminologies and nomenclatures. “Currently, the quantum hardware design cycle spans multiple tools in multiple domains, in a discordant fashion with multiple gaps in between,” says Mohamed Hassan, quantum solutions planning lead for Keysight. “These are typically filled by extra effort that is highly dependent on the knowledge and experience of the designer. It presents a steep knowledge barrier and keeps many engineers out of this emerging field. It is very different from how the current mature EDA design cycle is devised, for instance, for designing integrated circuits. Quantum EDA is envisioned to close these gaps, streamline the design cycle, reduce the knowledge barrier, and enable many engineers to jump into this new field.”

Conclusion
We are entering a period of high velocity change caused by the need to find new ways to get more out of things that already exist. “Physics defines it, manufacturing complexity limits it,” says Hand. “What does it mean to be a semiconductor engineer? There will continue to be a need for incredibly focused people in certain domains, but you’ll start to see a lot more flexibility in what it means to be a semiconductor engineer.”

3D-IC is a testing ground for how adaptable the semiconductor industry is. “The market is still in the formative stage,” says Swinnen. “It’s not clear and different people approach it differently.”

But it’s possible the solutions adopted by the chip industry will be those that cause the least organizational change, even if they are not the best solutions.

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