Creating A Moore’s Law For AI Scaling


Key Takeaways: AI scalability will require full-stack co-optimization, not just bigger data centers. AI workloads require a 10X compute efficiency gain over 10 years, making collaboration across algorithms, architectures, devices, packaging, and communication fabrics essential to deliver a 10X improvement in compute efficiency over the next decade.  Edge AI chips are moving to leadi... » read more

How To Build Billions of Bumps


Key Takeaways: Hybrid bonding can result in a package containing billions (and eventually trillions) of connections. Building that many connections successfully requires extreme process uniformity across a wafer. Inspection isn’t practical, and test benefits from internal test mechanisms. Hybrid bonding allows unprecedented signal pitch, but fully populating dies and inter... » read more

Chip Industry Technical Paper Roundup: June 16


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads 🔗 University of Wisconsin-Madison, AMD Beyond Silicon: Materials, Mechanisms, and Methods for Physical Neural Computing 🔗 University of Lübeck, TU Hamburg InjectV: M... » read more

Modeling Multi-GPU Traffic For Distributed AI Workloads (UW Madison, AMD)


Researchers from University of Wisconsin-Madison and AMD Research and Advanced Development published a technical paper titled “Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads.” Abstract: “As distributed AI workloads grow in scale, multi-GPU systems have become essential for training large models. Although techniques like kernel fusion and overlapping... » read more

Chip Industry Week In Review


Notable deals Cadence and Intel Foundry inked a multi-year agreement to advance design technology co-optimization and create PDKs for Intel Foundry's 14A process. Nvidia and SK hynix announced a multi-year partnership to co-develop memory technology for AI infrastructure and physical AI. Teradyne unveiled an integrated test cell solution with TEL that supports known-good device scree... » read more

Chip Industry Technical Paper Roundup: Jun. 2


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Physical Foundation Models: Fixed HW implementations of large-scale neural networks 🔗 Yale University, Cornell University, Boston University, NTT Research Understanding Inference Scaling for LLMs: Bottlenecks, Trade-offs, and Performance Princip... » read more

Improving GPU Energy Efficiency With Component-Level Power Management (AMD)


Researchers from AMD released “CompPow: A Case for Component-level GPU Power Management”. Abstract “The ever increasing demand for ML-driven intelligence in a wide spectrum of domains has led to ubiquity of GPUs. At the same time, GPUs are notorious for their power consumption needs and often dominate power allocation in a typical ML datacenter. While datacenter-level power opti... » read more

Chip Industry Week In Review


Advanced nodes and packaging AMD announced more than $10B in Taiwan ecosystem investments to scale advanced packaging manufacturing for AI infrastructure. The effort includes EFB-based 2.5D packaging collaborations with ASE and others. AMD also announced the start of its production ramp of its Venice processors on TSMC's 2nm process. Lam Research established a panel-level packaging cen... » read more

Chip Industry Week in Review


Global The U.S. created a licensing path for Nvidia H200 shipments in January and has since approved sales to 10 Chinese companies, but so far no shipments have been confirmed, reports Reuters. With a looming end-of-year expiration, SIA, SEMI, and other business groups are urging Congress to extend the US semiconductor tax credit and expand it to cover semiconductor design and other act... » read more

Chip Industry Week In Review


Acquisitions and business pivots Teradyne acquired Israel-based TestInsight, a semiconductor test provider with pattern conversion, validation, and virtual test capabilities. Credo plans to acquire DustPhotonics, a developer of silicon photonics PICs for optical transceivers. Molex plans to acquire Teramount, a provider of detachable, passive-alignment fiber-to-chip connectivity solu... » read more

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