Chip Industry Technical Paper Roundup: June 16

Multi-GPU traffic modeling; physical neural computing; RISC-V fault injection; automotive CAN timing analysis; EUV source optimization; lithography defect detection; dual-beam EUV efficiency.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Eidola: Modeling Multi-GPU Network Communication Traffic in Distributed AI Workloads 🔗 University of Wisconsin-Madison, AMD
Beyond Silicon: Materials, Mechanisms, and Methods for Physical Neural Computing 🔗 University of Lübeck, TU Hamburg
InjectV: Modeling Fault Injection Attacks in RISC-V Simulation Environment 🔗 Politecnico di Torino, CEA-List
A Cross-Validated DSPN and Worst-Case Response-Time Framework for Timing Analysis of Automotive CAN Networks 🔗 National Yang Ming Chiao Tung University, Chung Yuan Christian University
Optimization of EUV output by experimentally validated radiation-hydrodynamic simulations across a broad laser parameter space 🔗 The University of Osaka, National Institute for Fusion Science, National Institutes for Quantum Science and Technology, Osaka Metropolitan University
Failure-Aware Refinement of Vision-Language Model for Lithography Defect Detection 🔗 Hanyang University, Korea University, Korea Institute of Industrial Technology
40% boost in extreme ultraviolet conversion efficiency via simultaneous dual-beam 2-µm laser irradiation 🔗 Utsunomiya University, RIKEN, The University of Tokyo, Tohoku University

Find more semiconductor research papers here.

 

 



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