tag: Hanyang University

Chip Industry Technical Paper Roundup: Sept. 24
By Linda Christensen - 24 Sep, 2024 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=358 /] More ReadingTechnical Paper Library home » read more

Models for Both Strained and Unstrained GAA FETs Using Neural Networks
By Technical Paper Link - 23 Sep, 2024 - Comments: 0

A new technical paper titled "Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach" was published by researchers at Hanyang University and Alsemy Inc. Abstract "Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D... » read more

Research Bits: Sept. 3
By Jesse Allen - 03 Sep, 2024 - Comments: 0

3D printing of specialized antennas, sensors Researchers from the National University of Singapore developed a 3D printing technique that can be used to create three dimensional, self-healing electronic circuits. Called tension-driven CHARM3D, the technique enables the 3D printing of free-standing metallic structures without requiring support materials and external pressure. It uses Field�... » read more

Chip Industry Week In Review
By The SE Staff - 31 May, 2024 - Comments: 0

JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Sidestepping Lithography In Chip Manufacturing
By Katherine Derbyshire - 23 May, 2024 - Comments: 0

Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Research Bits: July 18
By Jesse Allen - 18 Jul, 2023 - Comments: 0

Miniaturized ferroelectric FETs Researchers from the University of Pennsylvania, Hanyang University, King Abdulaziz University, King Abdullah University of Science and Technology, and University of Tokyo proposed a new ferroelectric FET (FE-FET) design with improved performance for both computing and memory. The transistor layers the two-dimensional semiconductor molybdenum disulfide (MoS2)... » read more

Chip Industry’s Technical Paper Roundup: June 5
By Linda Christensen - 05 Jun, 2023 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=105 /] More Reading Technical Paper Library home » read more

ALD-Oxide Semiconductors: Summary, Benefits And Challenges
By Technical Paper Link - 31 May, 2023 - Comments: 0

A technical paper titled "Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook" was published by researchers at Hanyang University. "In this review, to introduce ALD-oxide semiconductors, we provide: (a) a brief summary of the history and importance of ALD-based oxide semiconductors in industry, (b) a discussion of the benefits of ALD for oxide... » read more

Chip Industry’s Technical Paper Roundup: Nov. 21
By Linda Christensen - 21 Nov, 2022 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=65 /] » read more

High Performance Memory: Novel Lateral Double Magnetic Tunnel Junction (MTJ) With An Orthogonal Polarizer
By Technical Paper Link - 17 Nov, 2022 - Comments: 0

A new technical paper titled "Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory" was published by researchers at Hanyang University. Find the technical paper here. Published November 2022. Sin, S., Oh, S. Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory.... » read more

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