Chip Industry Week In Review


JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

Sidestepping Lithography In Chip Manufacturing


Rising lithography costs, shrinking feature sizes, and the need for an alternative to copper are collectively spurring new interest in area-selective deposition. An extension of atomic layer deposition, ASD seeks to build circuit features from the bottom up, without relying on lithography. Lithography will remain a critical tool for the foreseeable future. But it has long been the most expen... » read more

Research Bits: July 18


Miniaturized ferroelectric FETs Researchers from the University of Pennsylvania, Hanyang University, King Abdulaziz University, King Abdullah University of Science and Technology, and University of Tokyo proposed a new ferroelectric FET (FE-FET) design with improved performance for both computing and memory. The transistor layers the two-dimensional semiconductor molybdenum disulfide (MoS2)... » read more

Chip Industry’s Technical Paper Roundup: June 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=105 /] More Reading Technical Paper Library home » read more

ALD-Oxide Semiconductors: Summary, Benefits And Challenges


A technical paper titled "Atomic layer deposition for nanoscale oxide semiconductor thin film transistors: review and outlook" was published by researchers at Hanyang University. "In this review, to introduce ALD-oxide semiconductors, we provide: (a) a brief summary of the history and importance of ALD-based oxide semiconductors in industry, (b) a discussion of the benefits of ALD for oxide... » read more

Chip Industry’s Technical Paper Roundup: Nov. 21


New technical papers added to Semiconductor Engineering’s library this week. [table id=65 /] » read more

High Performance Memory: Novel Lateral Double Magnetic Tunnel Junction (MTJ) With An Orthogonal Polarizer


A new technical paper titled "Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory" was published by researchers at Hanyang University. Find the technical paper here. Published November 2022. Sin, S., Oh, S. Lateral double magnetic tunnel junction device with orthogonal polarizer for high-performance magnetoresistive memory.... » read more

Technical Paper Round-Up: April 5


Neuromorphic chips, transistor defect detection, quantum, pellicles, BEV mobile charging, copper wire bonding, LrWPAN, batteries and superconductivity top the past week's technical papers. They also point to a rising level of government investment, and collaborations between schools that historically haven't worked closely together, including one that involves schools on different continents. ... » read more

Investigation of the Resistivity and Emissivity of a Pellicle Membrane for EUV Lithography


New technical paper from Hanyang University and University of Texas at Dallas. Abstract "A pellicle is a thin membrane structure that protects an extreme ultraviolet (EUV) mask from contamination during the exposure process. However, its limited transmittance induces unwanted heating owing to the absorption of EUV photons. The rupture of the EUV pellicle can be avoided by improving its ther... » read more

Gearing Up For High-NA EUV


The semiconductor industry is moving full speed ahead to develop high-NA EUV, but bringing up this next generation lithography system and the associated infrastructure remains a monumental and expensive task. ASML has been developing its high-numerical aperture (high-NA) EUV lithography line for some time. Basically, high-NA EUV scanners are the follow-on to today’s EUV lithography systems... » read more

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