Research Bits: Nov. 26


Hydrogel NAND gate Researchers from McMaster University and the University of Pittsburgh created a functionally complete NAND gate in a soft material using only beams of visible light. The NAND logic operation was completed by shining three self-trapped light beams into a photoresponsive merocyanine-functionalized hydrogel that is capable of performing compute tasks in the material itself w... » read more

Chip Industry Technical Paper Roundup: August 5


New technical papers recently added to Semiconductor Engineering’s library: [table id=460 /] Find more semiconductor research papers here. » read more

Challenges And Outlook of Photonic-Integrated Circuit Packaging (Hanyang Univ.)


A new technical paper titled "Advanced Optical Integration Processes for Photonic-Integrated Circuit Packaging" was published by researchers at Hanyang University. Excerpt "This review discusses the latest developments in photonic integrated chip packaging at the component, chip, and system levels. It also highlights the current issues and challenges of these technologies and provides futur... » read more

Chip Industry Technical Paper Roundup: Apr. 29


New technical papers recently added to Semiconductor Engineering’s library: [table id=424 /] Find more semiconductor research papers here. » read more

Differences In The Lithographic Impact Of Particles On The Pellicle Surface Depending On Type Of EUV Mask Pattern


A new technical paper titled "Impact of Sn Particle-Induced Mask Diffraction on EUV Lithography Performance Across Different Pattern Types" was published by Hanyang University and Paul Scherrer Institute. Abstract "This study investigates the differences in the lithographic impact of particles on the pellicle surface depending on the type of extreme ultraviolet (EUV) mask pattern. Using a... » read more

Research Bits: Feb. 25


Recording synaptic connections Researchers from Harvard University built a silicon chip capable of recording synaptic signals from a large number of neurons and used it to catalogue more than 70,000 synaptic connections from about 2,000 rat neurons. They hope the device is a step in creating a detailed synaptic connection map of the brain. The chip contains an array of 4,096 microhole elect... » read more

Chip Industry Technical Paper Roundup: Sept. 24


New technical papers recently added to Semiconductor Engineering’s library: [table id=358 /] More ReadingTechnical Paper Library home » read more

Models for Both Strained and Unstrained GAA FETs Using Neural Networks


A new technical paper titled "Impact of Strain on Sub-3 nm Gate-all-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach" was published by researchers at Hanyang University and Alsemy Inc. Abstract "Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. The model was trained using 3D... » read more

Research Bits: Sept. 3


3D printing of specialized antennas, sensors Researchers from the National University of Singapore developed a 3D printing technique that can be used to create three dimensional, self-healing electronic circuits. Called tension-driven CHARM3D, the technique enables the 3D printing of free-standing metallic structures without requiring support materials and external pressure. It uses Field�... » read more

Chip Industry Week In Review


JEDEC and the Open Compute Project rolled out a new set of guidelines for standardizing chiplet characterization details, such as thermal properties, physical and mechanical requirements, and behavior specs. Those details have been a sticking point for commercial chiplets, because without them it's not possible to choose the best chiplet for a particular application or workload. The guidelines ... » read more

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