AI-aided chip design; Cu-barrier properties of 2D WS2 films; safe autonomous driving; ultra-low-bit LLM models; out-of-band power side-channel detection; MFMIS FeTFETs for CIM HW accelerators; SNNs on neuromorphic HW; oxide semiconductor for advanced memory architectures.
New technical papers recently added to Semiconductor Engineering’s library:
| Technical Paper | Research Organizations |
|---|---|
| ChipBench: A Next-Step Benchmark for Evaluating LLM Performance in AI-Aided Chip Design | UCSD and Columbia University |
| Enhancing Cu-barrier properties of 2D-WS2 barriers: The role of grain size and surface passivation | NUS, AIXTRON, IMiF and Applied Materials |
| Chiplet Fundamentals For Engineers: eBook | Semiconductor Engineering |
| Towards Safe Autonomous Driving: A Real-Time Motion Planning Algorithm on Embedded Hardware | TU Munich |
| Pushing the Envelope of LLM Inference on AI-PC and Intel GPUs | Intel |
| Out-of-Band Power Side-Channel Detection for Semiconductor Supply Chain Integrity at Scale | Cornell University |
| Impact of Random Phase Distribution on Ferroelectric Tunnel Field-Effect Transistors With Mitigation Strategies for Compute-in-Memory Applications | Seoul National University |
| A Case for Hypergraphs to Model and Map SNNs on Neuromorphic Hardware | Politecnico di Milano |
| Oxide Semiconductor for Advanced Memory Architectures: Atomic Layer Deposition, Key Requirement and Challenges | Hanyang University and imec |
Find more semiconductor research papers here.
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