Chip Industry Week In Review


SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Memristor Crossbar Architecture for Encryption, Decryption and More


A new technical paper titled "Tunable stochastic memristors for energy-efficient encryption and computing" was published by researchers at Seoul National University, Sandia National Laboratories, Texas A&M University and Applied Materials. Abstract "Information security and computing, two critical technological challenges for post-digital computation, pose opposing requirement... » read more

Chip Industry Week In Review


By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

Chip Industry’s Technical Paper Roundup: November 6


New technical papers added to Semiconductor Engineering’s library this week. [table id=162 /] More Reading Technical Paper Library home » read more

Improving The Retention Characteristics Of 3D NAND Flash Memories


A technical paper titled “3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer” was published by researchers at Myongji University, Soongsil University, and Seoul National University. Abstract: "To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeat... » read more

Chip Industry’s Technical Paper Roundup: August 22


New technical papers added to Semiconductor Engineering’s library this week. [table id=129 /]   More Reading Technical Paper Library home » read more

A Chiplet-Based Fully Homomorphic Encryption Accelerator


A technical paper titled “CiFHER: A Chiplet-Based FHE Accelerator with a Resizable Structure” was published by researchers at Seoul National University. Abstract: "Fully homomorphic encryption (FHE) is in the spotlight as a definitive solution for privacy, but the high computational overhead of FHE poses a challenge to its practical adoption. Although prior studies have attempted to desig... » read more

Chip Industry’s Technical Paper Roundup: July 12


New technical papers recently added to Semiconductor Engineering’s library: [table id=117 /] (more…) » read more

DRAM Translation Layer, Mechanism for Flexible Address Mapping and Data Migration Within CXL-Based Memory Devices


A technical paper titled “DRAM Translation Layer: Software-Transparent DRAM Power Savings for Disaggregated Memory” was published by researchers at Seoul National University. Abstract: "Memory disaggregation is a promising solution to scale memory capacity and bandwidth shared by multiple server nodes in a flexible and cost-effective manner. DRAM power consumption, which is reported to be... » read more

Chip Industry’s Technical Paper Roundup: June 20


New technical papers added to Semiconductor Engineering’s library this week. [table id=112 /] » read more

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