Chip Industry Week In Review

By The SE Staff - 14 Jun, 2024 - Comments: 0

Samsung unveiled its latest 2nm and 4nm process nodes, plus its AI solutions during the Samsung Foundry Forum. The company also introduced an aggressive roadmap for the next few years that includes 3D-ICs with logic-on-logic, starting in 2025; custom HBM with built-in logic; backside power delivery on 2nm technology in 2027; and co-packaged optics. In presentations at the event, the company als... » read more

Chip Industry Week In Review

By The SE Staff - 24 May, 2024 - Comments: 0

Absolics, an affiliate of Korea materials company SKC, will receive up to $75 million in direct funding under the U.S. CHIPS Act for the construction of a 120,000 square-foot facility in Covington, Georgia, for glass substrates in advanced packaging. imec will host a €2.5 billion (~$2.72B) pilot line for researching chips beyond 2nm, partially funded through the EU Chips Act. imec CEO Luc ... » read more

Chip Industry Technical Paper Roundup: May 21

By Linda Christensen - 21 May, 2024 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=227 /] More ReadingTechnical Paper Library home » read more

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer

By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enh... » read more

Chip Industry Technical Paper Roundup: April 30

By Linda Christensen - 30 Apr, 2024 - Comments: 0

These new technical papers were recently added to Semiconductor Engineering’s library. [table id=222 /] Find more technical papers here. » read more

Chip Industry Week In Review

By The SE Staff - 19 Apr, 2024 - Comments: 0

SK hynix and TSMC plan to collaborate on HBM4 development and next-generation packaging technology, with plans to mass produce HBM4 chips in 2026. The agreement is an early indicator for just how competitive, and potentially lucrative, the HBM market is becoming. SK hynix said the collaboration will enable breakthroughs in memory performance with increased density of the memory controller at t... » read more

Memristor Crossbar Architecture for Encryption, Decryption and More

By Technical Paper Link - 16 Apr, 2024 - Comments: 0

A new technical paper titled "Tunable stochastic memristors for energy-efficient encryption and computing" was published by researchers at Seoul National University, Sandia National Laboratories, Texas A&M University and Applied Materials. Abstract "Information security and computing, two critical technological challenges for post-digital computation, pose opposing requirement... » read more

Chip Industry Week In Review

By The SE Staff - 23 Feb, 2024 - Comments: 0

By Jesse Allen, Gregory Haley, and Liz Allan Intel officially launched Intel Foundry this week, claiming it's the "world's first systems foundry for the AI era." The foundry also showed off a more detailed technology roadmap down to expanded 14A process technology. Intel CEO Pat Gelsinger noted the foundry will be separate from the chipmaker, utilize third-party chiplets and IP, and leverage... » read more

Chip Industry’s Technical Paper Roundup: November 6

By Liz Allan - 06 Nov, 2023 - Comments: 0

New technical papers added to Semiconductor Engineering’s library this week. [table id=162 /] More Reading Technical Paper Library home » read more

Improving The Retention Characteristics Of 3D NAND Flash Memories

By Technical Paper Link - 31 Oct, 2023 - Comments: 0

A technical paper titled “3D NAND Flash Memory Cell Current and Interference Characteristics Improvement With Multiple Dielectric Spacer” was published by researchers at Myongji University, Soongsil University, and Seoul National University. Abstract: "To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeat... » read more

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tag: Seoul National University

Chip Industry Week In Review

Chip Industry Week In Review

Chip Industry Technical Paper Roundup: May 21

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer

Chip Industry Technical Paper Roundup: April 30

Chip Industry Week In Review

Memristor Crossbar Architecture for Encryption, Decryption and More

Chip Industry Week In Review

Chip Industry’s Technical Paper Roundup: November 6

Improving The Retention Characteristics Of 3D NAND Flash Memories

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