How Property Specification Language (PSL) and SystemVerilog Assertions (SVA) assertion semantics can be extended to, and evaluated within, a SPICE-based simulator.
Assertion-based verification is a key aspect of any complete SoC or Silicon Realization flow. In this paper, we discuss how PSL (Property Specification Language)/SVA (System-V erilog Assertions) assertion semantics are extended for the first time to SPICE (Simulation Program with Integrated Circuit Emphasis)-level netlists and evaluated within a SPICE simulator, and present multiple examples and simulation results. Both inline pragma-based assertions (within SPICE subcircuits) and separate vunit/bind file based assertion methodologies (which reference objects within SPICE subcircuits) are covered.
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