Custom Designs, Custom Problems


Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

Challenges At 3/2nm


David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

Power And Performance Optimization At 7/5/3nm


Semiconductor Engineering sat down to discuss power optimization with Oliver King, CTO at Moortec; João Geada, chief technologist at Ansys; Dino Toffolon, senior vice president of engineering at Synopsys; Bryan Bowyer, director of engineering at Mentor, a Siemens Business; Kiran Burli, senior director of marketing for Arm's Physical Design Group; Kam Kittrell, senior product management group d... » read more

The Criticality Of The E/E Architecture


Modern vehicles are highly sophisticated systems incorporating electrical, electronic, software and mechanical components. Mechanical systems are giving way to advanced software and electronic devices, driving automakers to innovate and differentiate their vehicles via the electric and electronic (E/E) architecture. Future architectures need to be scalable across vehicle platforms, flexible to ... » read more

Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Software In Inference Accelerators


Geoff Tate, CEO of Flex Logix, talks about the importance of hardware-software co-design for inference accelerators, how that affects performance and power, and what new approaches chipmakers are taking to bring AI chips to market. » read more

Survival Of The Cheapest?


We all want the best solution to win, but that rarely happens. History is littered with products that were superior to the alternatives and yet lost out to a lessor rival. I am sure several examples are going through your mind without me having to list them. It is normally the first to volume that wins, often accelerated by copious amounts of marketing dollar to help push it against headwinds. ... » read more

Chiplets, Faster Interconnects, More Efficiency


Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

The Automation Of AI


Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Designing An AI SoC


Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

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