Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Software In Inference Accelerators


Geoff Tate, CEO of Flex Logix, talks about the importance of hardware-software co-design for inference accelerators, how that affects performance and power, and what new approaches chipmakers are taking to bring AI chips to market. » read more

Survival Of The Cheapest?


We all want the best solution to win, but that rarely happens. History is littered with products that were superior to the alternatives and yet lost out to a lessor rival. I am sure several examples are going through your mind without me having to list them. It is normally the first to volume that wins, often accelerated by copious amounts of marketing dollar to help push it against headwinds. ... » read more

Chiplets, Faster Interconnects, More Efficiency


Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

The Automation Of AI


Semiconductor Engineering sat down to discuss the role that EDA has in automating artificial intelligence and machine learning with Doug Letcher, president and CEO of Metrics; Daniel Hansson, CEO of Verifyter; Harry Foster, chief scientist verification for Mentor, a Siemens Business; Larry Melling, product management director for Cadence; Manish Pandey, Synopsys fellow; and Raik Brinkmann, CEO ... » read more

Designing An AI SoC


Susheel Tadikonda, vice president of networking and storage at Synopsys, looks at how to achieve economies of scale in AI chips and where the common elements are across all the different architectures. https://youtu.be/fm0kxnj3DuM » read more

Using Memory Differently


Chip architects are beginning to rewrite the rules on how to choose, configure and use different types of memory, particularly for chips with AI and some advanced SoCs. Chipmakers now have a number of options and tradeoffs to consider when choosing memories, based on factors such as the application and the characteristics of the memory workload, because different memory types work better tha... » read more

Concurrent Test


Derek Wu, senior staff applications engineer at Advantest, looks at the need for doing multiple tests at the same time as chip designs become more complex, increasingly heterogeneous, and much more difficult to test at advanced nodes. https://youtu.be/-8inbjX_af0       __________________________________ See more tech talk videos here. » read more

Inferencing In Hardware


Cheng Wang, senior vice president of engineering at Flex Logix, examines shifting neural network models, how many multiply-accumulates are needed for different applications, and why programmable neural inferencing will be required for years to come. https://youtu.be/jb7qYU2nhoo         See other tech talk videos here. » read more

Computing Way Outside Of A Box


Mike Muller, CTO of Arm, sat down with Semiconductor Engineering to talk about changing boundaries between client and server machines, the end of Moore's Law and the impact of machine learning on chip architectures. What follows are excerpts of that conversation. SE: Are the lines blurring between what's considered a client device and what's considered a server? Muller: It's less about a ... » read more

← Older posts Newer posts →