tag: architecture

The Next Big Chip Companies
By Ed Sperling - 05 Oct, 2018 - Comments: 1

Rambus’ Mike Noonen looks at why putting everything on a single die no longer works, what comes after Moore’s Law, and what the new business model looks like for chipmakers. https://youtu.be/X6Kca8Vm-wA » read more

Intel’s Next Move
By Ed Sperling - 11 Sep, 2018 - Comments: 0

Gadi Singer, vice president and general manager of Intel's Artificial Intelligence Products Group, sat down with Semiconductor Engineering to talk about Intel's vision for deep learning and why the company is looking well beyond the x86 architecture and one-chip solutions. SE: What's changing on the processor side? Singer: The biggest change is the addition of deep learning and neural ne... » read more

Architects Firmly In Control
By Ed Sperling - 23 Aug, 2018 - Comments: 0

Moore's Law isn't dead, but it certainly isn't what it used to be. While there may be three or four more generations of node shrinks ahead, the power/performance benefits of scaling are falling off. This is evident in new chip architectures that were introduced at this year's Hot Chips conference. Originally started to show off the latest CPUs and co-processors, in past years the focus has b... » read more

Architecture, Materials And Software
By Ed Sperling - 12 Apr, 2018 - Comments: 0

AI, machine learning and autonomous vehicles will require massive improvements in performance, at the same power consumption level (or better), over today's chips. But it's obvious that the usual approach of shrinking features to improve power/performance isn't going to be sufficient. Scaling will certainly help, particularly on the logic side. More transistors are needed to process a huge i... » read more

Smaller, Faster, Cheaper—But Different
By Ed Sperling - 22 Mar, 2018 - Comments: 0

The old mantra of "smaller, faster, cheaper" has migrated from the chip level to the electronic system level, raising some interesting questions about where the real value is being generated. Smaller as it pertains to gate size, line widths and spaces, will continue in an almost straight line for at least the next decade. The ability to print three-dimensional features on a nanoscale using E... » read more

Verification Of Functional Safety
By Brian Bailey - 25 Jan, 2018 - Comments: 4

Functional safety is becoming a key part of chip design, and an increasingly problematic one for many engineering teams. Functional safety for electrical and electronic systems is nothing new. It has been an important element of the military, aerospace and medical industries for many years. But the growing importance of functional safety within the automobile industry presents a number o... » read more

Tech Talk: Verification
By Ed Sperling - 30 Nov, 2017 - Comments: 0

Frank Schirrmeister, Cadence's senior group director for verification platforms, talks about what's changing in verification with 5G, machine learning, greater connectivity, advanced packaging, and the growing need to build security into designs. https://youtu.be/GMF8BkmdJzE » read more

The Perfect (Silicon) Marriage… Yes, It Exists
By Rajesh Ramanujam - 27 Jul, 2017 - Comments: 0

Nope, this is not Dr. Phil masquerading as a tech blogger, trying to penetrate the semiconductor market. I am no Dr. Phil, but today, rather than expound on interconnect IP and how it relates to the various trends, applications, markets, etc., I would like to tell you a story about a relationship and share an experience with one of our customers, a leading manufacturer of autonomous systems. ... » read more

Security: Losses Outpace Gains
By Ed Sperling - 06 Apr, 2017 - Comments: 0

Paul Kocher, chief scientist in [getentity id="22671" e_name="Rambus'"] Cryptography Research Division, sat down with Semiconductor Engineering to discuss the new threats to security, artificial intelligence and machine learning, and how to engineer a secure system. What follows are excerpts of that conversation. SE: Where are we with security? It seems that rather than getting better, thing... » read more

Power State Switching Gets Tougher
By Ann Mutschler - 12 Jan, 2017 - Comments: 0

Power state switching delay is a key factor in minimizing power, and getting it right frequently means the difference between a successful design and a dead chip. But tradeoffs are intricate, complex and often involve judgment calls, making this a place where designs can go completely awry. For years, traditional, full-swing [gettech id="31093" comment="CMOS"] process technologies were used ... » read more

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