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Making Chips At 3nm And Beyond

Lots of new technologies, problems and uncertainty as device scaling continues.

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Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that.

Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issues and the unforeseen pandemic outbreak, according to analysts. COVID-19 has slowed the momentum and impacted the sales in the IC industry.

This, in turn, is likely to push back the roadmaps beyond 3nm. Nevertheless, the current climate hasn’t stopped the semiconductor industry. Today, foundries and memory makers are running at relatively high fab utilization rates.

Behind the scenes, meanwhile, foundries and their customers continue to develop their 3nm and 2nm technologies, which are now slated for roughly 2022 and 2024, respectively. Work is also underway for 1nm and beyond, but that’s still far away.

Starting at 3nm, the industry hopes to make the transition from today’s finFET transistors to gate-all-around FETs. At 2nm and perhaps beyond, the industry is looking at current and new versions of gate-all-around transistors.

At these nodes, chipmakers will likely require new equipment, such as the next version of extreme ultraviolet (EUV) lithography. New deposition, etch and inspection/metrology technologies are also in the works.

Needless to say, the design and manufacturing costs are astronomical here. The design cost for a 3nm chip is $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, according to IBS. Beyond those nodes, it’s too early to say how much a chip will cost.

Not all designs require advanced nodes. In fact, rising costs are prompting many to explore other options, such as advanced packaging. One way to get the benefits of scaling is by putting advanced chips in a package.

Semiconductor Engineering has taken a look at what’s ahead in terms of the next transistors, fab tools, materials, packaging and photonics.

New transistors and materials
Transistors, one of the key building blocks in chips, provide the switching functions in devices. For decades, chips based on planar transistors were the most advanced devices in the market.

At 20nm, planar transistors hit the wall. In response, Intel in 2011 moved to finFETs at 22nm, followed by the foundries at 16nm/14nm. In finFETs, the control of the current is accomplished by implementing a gate on each of the three sides of a fin.

With finFETs, chipmakers have continued with traditional chip scaling. But finFETs are expected to run out of steam when the fin width reaches 5nm, which will occur somewhere around the 3nm node. So at 3nm, select foundries in 2022 hope to migrate to a next-generation transistor called nanosheet FETs. A nanosheet FET falls under a category called gate-all-around FETs.

A nanosheet FET is an extension of a finFET. It’s a finFET on its side with a gate wrapped around it. Nanosheets will appear at 3nm and may extend to 2nm or beyond.


Figure 1: Planar transistors vs finFETs vs nanosheet FET. Source: Samsung

There are other options on the table that also fall into the gate-all-around category. For example, Imec is developing a forksheet FET for 2nm. In forksheet FETs, both nFET and pFET are integrated in the same structure. A dielectric wall separates the nFET and pFET. This is different from existing gate-all-around FETs, which use different devices for the nFETs and pFETs.

Forksheet FETs allow for a tighter n-to-p spacing and reduction in area scaling. Imec’s 2nm forksheet has a 42nm contacted gate pitch (CPP) and a 16nm metal pitch. In comparison, nanosheets have a 45nm CPP and 30nm metal pitch.

Complementary FETs (CFETs), another type of gate-all-around device, are also an option at 2nm and perhaps beyond. CFETs consist of two separate nanowire FETs (p-type and n-type). Basically, the p-type nanowire is stacked on top of an n-type nanowire.

“The concept of CFET consists in ‘folding’ the nFET on the pFET device, which eliminates the n-to-p separation bottleneck and, as a consequence, reduces the cell active area footprint by a factor two,” said Julien Ryckaert, program director at Imec, in a recent paper.

CFETs are promising. “When people look at gate-all-around technologies, and specifically stacked complementary nanowires (CFETs) and similar technologies, they see these enabling technologies as creating an inflection point toward 3nm, 2nm and 1nm logic scaling,” said David Fried, vice president of computational products at Lam Research/Coventor. “People are reviewing the stacked nanowire landscape trajectory along with the next steps to enable that transition. This is what people are thinking might be beyond 3nm. I don’t know that anybody is defining the nodes in that space, but these technologies might enable the next scaling trajectory at 3nm and beyond.”

CFETs and related transistors have some challenges, though. “The problems are the thermal processes,” said Jeffrey Smith, senior member of the technical staff at TEL. “You need to put a lot of metals down before the high-temperature processes. So you need to identify the maximum thermal limits for the barrier metals needed between the contact and the interconnect of the CFET.”

All told, CFETs will require time to develop because today there is very little silicon learning to draw upon, and lots of problems to solve. “CFET is promising, but it’s still early,” said Handel Jones, CEO of IBS. “A big problem is that even though the gate structures are enhanced, we need to enhance the MOL and the BEOL. Otherwise, the performance enhancements are limited.”

Manufacturing chips at 2nm/1nm brings up a whole slew of new issues, and new techniques and equipment will be required across a variety of different steps. This is evident in the thin films applied during manufacturing.

“When you start getting down to layers that are less than 5nm thick in spin-coat deposits, you are susceptible to small variations in surface energy,” said James Lamb, Corporate Technical Fellow at Brewer Science. “That may be from your substrate or it may be from your material. So you really need to be perfect in your wetting and substrate surface being coated, as well as the material you’re coating with, to not have any defects. These are thin enough where the interface dynamics dominate the film formation much like in self-assembly processes, and it’s very susceptible to minor changes.”

To put this in perspective, a 1nm film may have 5 to 8 atoms of thickness. Many of these films are in the range of 30 to 40 atoms.

“Laying that down, wetting the surface, and getting the material to adhere to that surface becomes a challenge,” said Lamb. “A key driver is the cleanliness of the materials. If you have any variation in the substrate, you’re going to get an anomaly or a localized thickness variation.”

New EUV scanners
Lithography, the art of patterning tiny features on chips, helps enable chip scaling. At 3nm and beyond, chipmakers likely will require a new version of EUV lithography called high-numerical aperture EUV (high-NA EUV).

An extension of today’s EUV, high-NA EUV is still in R&D. Targeted for 3nm in 2023, the mammoth-size tool is complex and expensive.

EUV is important for several reasons. For years, chipmakers used optical-based 193nm lithography scanners in the fab. With the help of multiple patterning, chipmakers have extended 193nm lithography down to 10nm/7nm. But at 5nm, the current lithographic technologies run out of steam.

That’s where EUV fits in. EUV enables chipmakers to pattern the most difficult features at 7nm and beyond. “Using EUV at 13.5nm wavelengths should make it easier and more viable,” said Aki Fujimura, CEO of D2S.

EUV has been a difficult technology to develop. Today, though, ASML is shipping its latest EUV scanner. Using a 13.5nm wavelength with a 0.33 NA lens, the system enables 13nm resolutions with a throughput of 170 wafers per hour.

At 7nm, chipmakers are patterning the tiny features using an EUV-based single patterning approach. Single patterning EUV will extend to roughly 30nm to 28nm pitches. Beyond that, chipmakers require EUV double patterning, which is a difficult process.

“Even if we apply multiple patterning techniques to EUV, overlay will be incredibly difficult,” said Doug Guerrero, senior technologist at Brewer Science.

Double patterning EUV is still an option at 5nm/3nm and beyond if it proves to be cost-effective. But to hedge their bets, chipmakers want high-NA EUV, enabling them to continue with the simpler single-patterning approach.

A high-NA EUV scanner is complex, though. The system features a radical 0.55 NA lens capable of 8nm resolutions. Instead of a traditional lens design, the high-NA tool will use an anamorphic lens. This lens supports 8X magnification in the scan mode and 4X in the other direction. As a result, the field size is reduced by one half. So in some cases, a chipmaker would process a chip on two different masks. Then, the masks are stitched together and printed on the wafer, which is a complex process.

There are other issues. The resists for high-NA aren’t available. Fortunately, the existing EUV mask tools can be leveraged for 3nm and beyond.

The industry, however, may require EUV mask blanks with new materials. This, in turn, requires faster mask blank ion beam deposition (IBD) tools. “We are working aggressively with our key customers to release several advanced features within our IBD system design that will address 3nm and beyond,” said Meng Lee, director of product marketing at Veeco.

All told, high-NA faces several challenges. “High-NA EUV is still several years away from reaching high-volume production capabilities,” said Patrick Ho, an analyst with Stifel Nicolaus. “ASML may begin to deliver beta systems in 2021. But as EUV has taught us, beta systems do not mean that high-volume production is around the corner.”

Molecular-level processing
Today’s chips are produced using various atomic-level processing tools. One such technology, called atomic layer deposition (ALD), deposits materials one layer at a time.

Atomic layer etch (ALE), a related technology, removes targeted materials at the atomic scale. Both ALD and ALE are used in logic and memory.

The industry also is working on advanced versions of ALD and ALE for the sub-3nm nodes. Area-selective deposition, an advanced self-aligned patterning technique, is one such technology. Combining novel chemistries with ALD or molecular layer deposition (MLD) tools, selective deposition involves a process of depositing materials and films in exact places. In theory, selective deposition can be used to deposit metals on metals and dielectrics on dielectrics on a device.

Potentially, it could reduce the number of lithography and etch steps in the flow. But area-selective deposition is still in R&D amid a slew of challenges.

Another technology on the horizon is molecular layer etch (MLE). “ALE has been around since the 1990s,” said Angel Yanguas-Gil, principal materials scientist at Argonne National Laboratory. “It was plasma-based, but there have been developments for inorganic materials involving isotropic atomic-layer etching, which is where we are today. Molecular layer etch is an extension of that for hybrid organic/inorganic materials. For the semiconductor industry, it provides a way of doing isotropic reduction of materials that could be used as masks for lithography.”

For chips developed in the low single-digit nodes, one of the big problems is the selective growth of devices. Also problematic is the removal of specific materials. So anomalies that show up in chips can be removed with some kind of etch, but at these geometries any material that is left over on a wafer can cause additional problems, such as a blockage in the mask.

“The industry has been looking at block copolymers as a way of producing these tightly patterned surfaces,” said Yangaus-Gil. “When you do the block copolymer approach, you get very nice lines, but they come with a lot of roughness. The exploration of this process relies on ALD precursors. People haven’t demonstrated yet that you can selectively grow masks. But if you had to bet on the next way to go, it probably will be in that direction.”

Nearly all of the commercial efforts in the past have focused on inorganic materials, which are denser and thinner than organic materials. But as more organic materials enter into the manufacturing processes, things get more complex.

“There will be tradeoffs between the isotropic nature and the saturation value that you get for the mask release, which in this process is higher in terms of thickness, even though the material is lower density,” Yangaus-Gil said. “With MLE, what we are doing is releasing a specific bond from the surface. What you have to keep in mind is how ordered the individual layers are, and how that affects accessibility to the bond you are targeting in the MLE process.”

Process control challenges
Inspection and metrology are also important. Inspection uses various systems to find defects in chips, while metrology is the art of measuring structures.

Inspection is split into two categories—optical and e-beam. Optical inspection tools are fast, but they have some resolution limits. E-beam inspection systems have better resolution, but they are slower.

So the industry has been developing multi-beam e-beam inspection systems, which in theory could find the most difficult defects at higher speeds.

ASML has developed an e-beam inspection tool with nine beams. However, chipmakers want a tool with a multitude of beams to speed up the process. It’s unclear if the industry will ever ship these tools. The technology still faces a number of challenges.

Metrology also faces some challenges. Today, chipmakers use various systems, such as CD-SEMs, optical CD and others, to measure structures. CD-SEMs take top-down measurements. Optical CD systems use polarized light to characterize structures.

A decade ago, many thought CD-SEMs and OCD would run out of steam. So the industry accelerated the development of several new metrology types, including an X-ray metrology technology called critical-dimension small-angle X-ray scattering (CD-SAXS). CD-SAXS uses variable-angle transmission scattering from a small beam size to provide the measurements. The X-rays have a wavelength less than 0.1nm.

It’s a non-destructive technique. “CD-SAXS conceptionally is a very simple measurement. An X-ray source sends a focused beam of X-rays through a sample with a periodic nanostructure and an X-ray camera takes an image of the scattered X-rays. The measurement is then repeated for a series of incident angles,” said Joseph Kline, a materials engineer at NIST. “The periodicity results in single-crystal scattering similar to what is obtained in protein crystallography. The scattering pattern can then be inversely solved to obtain the average shape of the electron density distribution of the periodic structure. The scattering calculation is a Fourier transform, so it is computationally easy for most structures. CD-SAXS can solve for CDs, disorder in the CD, and differences in electron density between layers (which can be related to composition). The main advantages of CD-SAXS over conventional OCD are that the optical constants are atomic properties independent of size, the small wavelength gives higher resolution and avoids many of the parameter correlation issues that OCD has, and the calculation is much simpler. CD-SAXS can also measure buried structures and optically opaque layers.”

Over the years, several entities have demonstrated promising results with CD-SAXS. In some cases, though, the X-rays are generated by a large synchrotron storage ring at an R&D facility.

This is impractical for a fab. For a fab tool, CD-SAXS requires compact X-ray sources. Several companies sell these tools, mostly for R&D. Intel, Samsung, TSMC and others have CD-SAXS tools in the lab.

The problem with fab-based CD-SAXS is that the X-ray source is limited and slow, which impacts throughput. “CD-SAXS gives you phenomenal profiles. Because it penetrates through the substrate, you can see layers of different materials,” said Dan Hutcheson, CEO of VLSI Research. “It’s a scatterometry-type technology like optical scatterometry, but it’s slow.”

Cost is also an issue. “It’s probably 5X or 10X more expensive. The cost-of-ownership is high compared to optical,” said Risto Puhakka, president of VLSI Research.

So chipmakers aren’t expected to insert CD-SAXS in the in-line monitoring flow for some time, at least for logic. “We typically forecast five years out,” Puhakka said.

CD-SAXS is making progress in memory. Today, in R&D, memory makers are using the technology to characterize hard masks and high-aspect ratio structures.

“For memory, the structures are deep. The scattering is good, so there is a clear roadmap to ~1 minute or less per site,” said Paul Ryan, director of product management at Bruker. “For logic, the technique is still in the concept phase, and there are expected to be challenges for the X-ray intensity.”

Fortunately, CD-SEM and OCD have extended further than previously thought and are being used today. Other X-ray metrology types are also used. But will they extend forever?

Packaging shifts
IC scaling, the traditional way of advancing a design, relies on shrinking different chip functions at each node and packing them onto a monolithic die. But IC scaling is becoming too expensive for many, and the performance and power benefits are diminishing at each node.

“From an economic standpoint, how many companies can afford silicon at the bleeding edge nowadays? That number is shrinking,” said Walter Ng, vice president of business management at UMC. “For the very, very high performance markets, there is always going to be that need. But in the supply chain, from a volume standpoint, the chasm is opening up in the middle. The very leading edge needs 7, 5 and maybe 3nm someday. But everyone else has slowed down quite a bit.”

While scaling remains an option for new designs, many are searching for alternatives like advanced packaging. Chiplets is another form of heterogenous integration.

Packaging is becoming more a viable option for several reasons. For example, while area is critical, particularly in AI applications where the speed of a chip depends on highly redundant arrays of processing elements and accelerators, the biggest benefits at each new node are derived from architectural changes and hardware-software co-design. It takes longer for a signal to travel from one end of a large chip to another over skinny wires than it does to travel vertically to another die using a high-speed interface.

This has prompted packaging houses and foundries to further improve the speed of packaged devices by improving the connections between devices, and improving the density of the packages themselves.

TSMC’s push to embed chiplets inside a package at the front-end-of-the-line (FEOL) is a case in point. The foundry plans to use advanced hybrid bonding techniques for what it calls system on integrated chips (SoIC).

That will be even faster than connecting chips together using a silicon interposer, which today is the state-of-the-art for this kind of approach. But silicon interposers also can be used as waveguides for photonics, both in-package and between packages, which adds yet another option for this approach.

“Right now, you see fiber within a server farm, which is east-west traffic,” said Rich Rice, senior vice president of business development at ASE. “You’re going to see the backplanes replaced. The fiber is not going through a module but directly to the server, and eventually to the package that the switch is on. It still has a lot of evolution to go, but we’ll see companies out there try to jump in to do the latest stuff sooner rather than later. That will accelerate the application of photonics. It will have more bandwidth, and it will get cheaper as we start to see more high-volume solutions.”

The advantage of light is that it requires less power than sending an electric signal over copper wires. “It’s still a way out in the future, but there are companies working on interposers that transmit light,” Rice said. “After that, you can interface with the chip with that, and it’s just a matter of getting those light signals into the side of the package.”

This is easier said than done, of course. Optical signals will drift as heat rises, so filters need to be calibrated to account for that drift. In addition, they can be interrupted by sidewall roughness in the waveguides. On the other hand, packaging with light is no longer just a distant research project.

There are other advantages in advanced packaging. Analog circuits can be developed at whatever node is ideal, and they can be re-used repeatedly without worrying about shrinking those devices.

In addition, the industry continues to make improvements in packaging for power semiconductors. In silicon carbide (SiC), for example, vendors integrate SiC power MOSFETs and other components in a power module. SiC itself has a higher breakdown field and a higher thermal conductivity than silicon.

Fig. 2: SiC MOSFET. Source: Cree

“What we and others are working on is how to optimize that module to take full advantage of silicon carbide. You have to know what you’re doing with a power module,” said John Palmour, CTO of Cree, in a recent interview. “Silicon carbide switches so fast versus silicon. There’s a lot of things you need to do within the package to actually get the performance out of it. In other words, if you use standard power module designs that are used for silicon, you’re only going to get about half of the performance you’re entitled to with SiC.”

Conclusion
The migration to 3nm will happen, although it might take longer than expected. The same is true for 2nm.

Beyond that, it’s unclear what will happen at 1nm. CFETs might be the way to go. On the other hand, chip scaling may end, or it may be limited to small high-performance, highly-specific chips or chiplets that require extremely high density.

In the near term, though, there is room for multiple technologies because no single technology can handle all applications.



4 comments

Allen Rasafar says:

Thank you Mark for this great coverage of technology…

Nicolas Dujarrier says:

Thanks Mark and Ed for the exploration of potential different technology options after 5nm node.

As of April 2020, I am skeptical about any node based of a 2D shrink by lithography after 3nm / 2nm (nanosheet / forksheet) because it will be too cost prohibitive for the meager power/performance gains compare to 7nm/5nm node.

In my humble opinion, if the design cost forecasted by IBS for a 3nm chip should be around $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, then I would think that companies that need the leading edge chips (Apple, Huawei, Qualcomm, AMD, Nvidia, Google, Amazon, Microsoft,…) would be financially better off by (collectively) investing to speed-up the development of the ongoing DARPA research program 3DSoC (2018 – 2022), that has the goal to layout the necessary ecosystem to design monolithic 3D chip based on carbon nanotubes with at least 50x performance improvement at power compare to a 7nm node chip, at a design cost similar to the design of a 7nm chip.

The budget allocated for the DARPA 3DSoC project is « only » $75 million. So instead of allocating $650 million or more to the design of 1 or several 3nm / 2nm chip, the companies that need leading edge performance would be better of (collectively) investing several $100 million to speed-up the development of the ecosystem to design monolithic 3D chip based on carbon nanotubes, and will then be able to design chip with better (or similar) performance at a design cost in the ballpark of a 7nm chip.

https://www.darpa.mil/attachments/3DSoCProposersDay20170915.pdf

https://youtu.be/6ir_–MgMJI

Therefore, even if the DARPA 3DSoC doesn’t reach all its goals, and for example, only reach a 5x improvement compare to a 7nm chip, in my view, the DARPA 3DSoC clearly has the potential to remove many of the most expensive hurdles, and open a new path for chip manufacturing (based on carbon nanotubes instead of silicon).

Nicolas DUJARRIER says:

Thanks Mark and Ed for the exploration of potential different technology options after 5nm node.

As of April 2020, I am skeptical about any node based of a 2D shrink by lithography after 3nm / 2nm (nanosheet / forksheet) because it will likely be too cost prohibitive for the meager power/performance gains compare to 7nm/5nm node.

In my humble opinion, if the design cost forecasted by IBS for a 3nm chip should be around $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, then I would think that companies that need the leading edge chips (Apple, Huawei, Qualcomm, AMD, Nvidia, Google, Amazon, Microsoft,…) would be financially better off by (collectively) investing to speed-up the development of the ongoing DARPA research program 3DSoC (2018 – 2022), that has the goal to layout the necessary ecosystem to design monolithic 3D chip based on carbon nanotubes with at least 50x performance improvement at power compare to a 7nm node chip, at a design cost similar to the design of a 7nm chip.

I think the budget allocated for the DARPA 3DSoC project is in the ballpark of a few $100 million. So instead of allocating $650 million or more to the design of 1 or several 3nm / 2nm chip, the companies that need leading edge performance would be better of (collectively) investing several $100 million to speed-up the development of the ecosystem to design monolithic 3D chip based on carbon nanotubes, and would then be able to design chip with better (or similar) performance than a silicon 3/2nm chip at a design cost in the ballpark of a 7nm chip.

Therefore, even if the DARPA 3DSoC research project doesn’t reach all its goals, and for example, only reach a 5x improvement compare to a 7nm chip, in my view, the DARPA 3DSoC clearly has the potential to remove many of the most expensive hurdles to open a new path for chip manufacturing based on carbon nanotubes instead of silicon, with performance equal or superior to a silicon CMOS 3nm / 2nm node while costing much less than a silicon CMOS 7nm/5nm chip design.

Mark LaPedus says:

Hi Nicolas,
Excellent points. Perhaps we should have included 3DSoC in this article. The 3DSoC program has more questions than answers, however. And it’s not exactly on the roadmap–yet.

I’ve written about this effort: DARPA’s 3DSoC project involves a two-layer 3D structure, which places ReRAM on carbon nanotube logic. Right now, it’s a 90nm process on 200mm wafers. Skyworks is the foundry here.

https://semiengineering.com/the-next-new-memories/

It’s a great idea, but there are several issues:
1) CNT devices have been in R&D for several years, but there are several challenges. We have been waiting for CNT logic and memory for years. No real production.
2) Purity of CNT materials.
3) Variation and alignment of CNTs in the fab.
4) Not sure about ReRAM on CNT. I could see CNT FETs. (CNT RAMs are different.)

I agree with you, however. It’s worth exploring. Intel, TSMC and others are looking at CNTs. During the short course at the recent IEDM event, TSMC talked about CNTs and the challenges. Many to overcome.

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