The Sub-2nm Paradox

By Ed Sperling - 01 Jun, 2026 - Comments: 2

Key Takeaways: Process variation and physics are changing semiconductor design, manufacturing, and economics at 2nm and below. Even though new manufacturing processes are being introduced, it's taking longer for them to mature. The focus for many chip designs is faster data movement and more efficient computing, rather than just relying on more transistors per mm2. At 2nm an... » read more

ANN Framework for Thermal-Aware Modeling of GAAFETs (NYCU)

By Technical Paper Link - 12 May, 2026 - Comments: 0

A new technical paper, "A Device-Physics-Informed Artificial Neural Network Approach for Thermal-Aware I-V and C-V Modeling of GAA FETs," was published by researchers at National Yang Ming Chiao Tung University. Abstract "This work introduces a device-physics-informed neural network framework for simultaneous modeling of thermal-aware I-V and C-V characteristics of gate-all-around (GAA) f... » read more

Precision In Depth: Extraction Workflows For CFETs And Buried Power Rails

By Karen Chow - 26 Mar, 2026 - Comments: 0

By Karen Chow, Sheetal Veronica, and Kunjesh Agashiwala In the heart of Manhattan, where land is scarce but demand is infinite, architects had to rethink the city grid. Instead of sprawling outward, they built upward with skyscrapers and carved subways below ground, inventing a “3D” city. Today’s chip designers face a similar dilemma: the two-dimensional plane of planar scaling is near... » read more

Extraction Challenges of CFET and Backside Power Delivery

By Siemens EDA - 25 Mar, 2026 - Comments: 0

The integration of complementary field-effect transistors (CFETs) and buried power rails (BPRs) is central to advancing semiconductor scaling for nodes at 3nm and below. CFETs achieve unprecedented device density by vertically stacking n-type and p-type transistors, while BPRs embed the power network within the silicon substrate to boost efficiency and minimize area usage. These advances drive ... » read more

2D Semiconductors Inch Forward

By Katherine Derbyshire - 19 Mar, 2026 - Comments: 0

Key Takeaways: Diffusing oxygen into 2D materials can improve adhesion properties. Channel-last processes can preserve most of the traditional gate-all-around process flow. Dual-gate MoS2 FETs with graphene contacts take advantage of layer transfer methods. Transition metal dichalcogenides (TMDs) have come a long way since exfoliated flakes were the state of the art, but the... » read more

Carrier Mapping in Sub-2nm Node NSFETs with SSRM (imec, KU Leuven)

By Technical Paper Link - 15 Feb, 2026 - Comments: 0

Researchers from imec and KU Leuven published "Carrier Mapping in Sub-2nm Node Nanosheet Transistors with Scanning Spreading Resistance Microscopy." Abstract "As the semiconductor industry transitions to gate-all-around architectures such as Nanosheet-FETs (NSFETs) for the 2nm node and beyond, controlling parasitic resistance through precise junction engineering is fundamental. This requi... » read more

Integrating vdW-Interface-Based high-κ Dielectrics On Both n- And p-Type 2D Semiconductors (Sungkyunkwan U., KAIST)

By Technical Paper Link - 08 Dec, 2025 - Comments: 0

A new technical paper "High-κ dielectric van der Waals integration on 2D semiconductors for three-dimensional complementary logic systems" was published by researchers at Sungkyunkwan University and KAIST. "This scalable methodology enables the vertical integration of complementary logic, demonstrated by complementary FET inverters and ring oscillators, establishing a promising route toward... » read more

Comparative Analysis of CFET and NSFET Architectures (TU Munich, IIT)

By Technical Paper Link - 14 Nov, 2025 - Comments: 0

A new technical paper titled "Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET" was published by researchers at TU Munich and Indian Institute of Technology. Abstract "This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature ... » read more

CMOS 2.0: Layered Logic For The Post-Nanosheet Era

By Gregory Haley - 24 Jul, 2025 - Comments: 0

The semiconductor industry has relied on a simple equation for more than five decades — shrink the transistor, pack more onto every wafer, and watch performance soar as costs plummet. While each new node delivered predictable gains in speed, power efficiency, and density, that formula is rapidly running out of steam. As transistors approach single-digit nanometer processes, manufacturing c... » read more

Wafer Bonding Mechanisms Using SiCN Films For Hybrid Bonding Applications In 3D Integration

By Technical Paper Link - 24 Jun, 2025 - Comments: 1

A new technical paper titled "Material-Mechanistic Interplay in SiCN Wafer Bonding for 3D Integration" was published by researchers at Yokohama National University, TEL, SK hynix, and University of Tsukuba. According to the paper: "Although much research has been conducted on wafer bonding methods compatible with the latest semiconductor manufacturing processes, discussions on the interface... » read more

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tag: CFETs