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tag: nanosheet FETs

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 1

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Inner Spacer Engineering to Improve Mechanical Stability in Channel-Release Process of Nanosheet FETs
By Technical Paper Link - 28 Aug, 2021 - Comments: 0

  Abstract "Mechanical stress is demonstrated in the fabrication process of nanosheet FETs. In particular, unwanted mechanical instability stemming from gravity during channel-release is covered in detail by aid of 3-D simulations. The simulation results show the physical weakness of suspended nanosheets and the impact of nanosheet thickness. Inner spacer engineering based on geometr... » read more

The Future Of Transistors And IC Architectures
By Mark LaPedus - 18 Mar, 2021 - Comments: 1

Semiconductor Engineering sat down to discuss chip scaling, transistors, new architectures, and packaging with Jerry Chen, head of global business development for manufacturing & industrials at Nvidia; David Fried, vice president of computational products at Lam Research; Mark Shirey, vice president of marketing and applications at KLA; and Aki Fujimura, CEO of D2S. What follows are excerpt... » read more

New Transistor Structures At 3nm/2nm
By Mark LaPedus - 25 Jan, 2021 - Comments: 12

Several foundries continue to develop new processes based on next-generation gate-all-around transistors, including more advanced high-mobility versions, but bringing these technologies into production is going to be difficult and expensive. Intel, Samsung, TSMC and others are laying the groundwork for the transition from today’s finFET transistors to new gate-all-around field-effect trans... » read more

Imec’s Plan For Continued Scaling
By Paul McLellan - 14 Jan, 2021 - Comments: 0

At IEDM in December, the opening keynote (technically "Plenary 1") was by Sri Samevadam of Imec. His presentation was titled "Towards Atomic Channels and Deconstructed Chips." He presented Imec's view of the future of semiconductors going forward, both Moore's Law (scaling) and More than More (advanced packaging and multiple die). It is always interesting to hear Imec's view of the world since... » read more

Finding Defects With E-Beam Inspection
By Mark LaPedus - 20 Aug, 2020 - Comments: 0

Several companies are developing or shipping next-generation e-beam inspection systems in an effort to reduce defects in advanced logic and memory chips. Vendors are taking two approaches with these new e-beam inspection systems. One is a more traditional approach, which uses a single-beam e-beam system. Others, meanwhile, are developing newer multi-beam technology. Both approaches have thei... » read more

Speeding Up The R&D Metrology Process
By Mark LaPedus - 16 Jul, 2020 - Comments: 0

Several chipmakers are making some major changes in the characterization/metrology lab, adding more fab-like processes in this group to help speed up chip development times. The characterization/metrology lab, which is generally under the radar, is a group that works with the R&D organization and the fab. The characterization lab is involved in the early analytical work for next-generati... » read more

Challenges In Stacking, Shrinking And Inspecting Next-Gen Chips
By Ed Sperling and Mark LaPedus - 21 May, 2020 - Comments: 0

Rick Gottscho, CTO of Lam Research, sat down with Semiconductor Engineering to discuss memory and equipment scaling, new market demands, and changes in manufacturing being driven by cost, new technologies, and the application of machine learning. What follows are excerpts of that conversation. SE: We have a lot of different memory technologies coming to market. What's the impact of that? ... » read more

Metrology Challenges For Gate-All-Around
By Mark LaPedus - 16 Apr, 2020 - Comments: 3

Metrology is proving to be a major challenge for those foundries working on processes for gate-all-around FETs at 3nm and beyond. Metrology is the art of measuring and characterizing structures in devices. Measuring and characterizing structures in devices has become more difficult and expensive at each new node, and the introduction of new types of transistors is making this even harder. Ev... » read more

Making Chips At 3nm And Beyond
By Mark LaPedus and Ed Sperling - 16 Apr, 2020 - Comments: 4

Select foundries are beginning to ramp up their new 5nm processes with 3nm in R&D. The big question is what comes after that. Work is well underway for the 2nm node and beyond, but there are numerous challenges as well as some uncertainty on the horizon. There already are signs that the foundries have pushed out their 3nm production schedules by a few months due to various technical issu... » read more

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