What’s Next For Transistors And Chiplets

Imec’s SVP drills down into GAA FETs, interconnects, chiplets, and 3D packaging.


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion.

SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging is playing a big role. What’s happening here?

Samavedam: Density scaling, which has been the basis for Moore’s Law, will continue. If you look at how the number of transistors in chips has evolved over the years, it follows Moore’s Law quite closely. Density scaling is happening as expected. But what we’re seeing is that you’re not getting the performance from general-purpose compute CPUs that we used to in the past. The node-to-node logic device performance has slowed down. So you will have to come up with new materials and device architectures to give you that additional boost in performance at the system level. At Imec, we’re also focused on STCO, or system technology co-optimization. There are two approaches to this. We have a bottom-up and a top-down approach. By bottom-up, what I mean is you look at technologies beyond just scaling to give you performance at a system level. For example, you may need a new cooling technology that enables you to break through the power wall and gives you a system-level performance. There are also different memory architectures and novel memories that give you a performance improvement in a machine learning system, for example. Then, you might have partitioning of the SoC (system-on-a-chip) into logic and memory and connecting them using 3D. These are instances of bottom-up STCO. We are starting to look at a top-down modeling of systems to identify specs for technologies that benefit most at the system level. This is the top-down approach to STCO. Because you’re not seeing the performance from pure scaling, we’ll have to look at new devices and STCO to get the system-level benefit.

SE: What other trends do you see?

Samavedam: The other trend that we observe is that CPUs, which have been the workhorse for general-purpose compute for years, are slowing down. We find more domain-specific architectures showing up. GPUs are a good example. You can look at GPU performance as a function of a number of operations per unit area or number of operations per unit watt. Just look at the GPUs from Nvidia and AMD, for example. They continue to do really well. They take advantage of scaling and they can pack tighter and more efficient cores for workloads that can be parallelized, like graphics processing or machine learning. They don’t show the same performance slowdown we’re seeing in CPUs. So we expect to see more domain-specific computer architectures going forward.

SE: On the transistor side, finFETs have been the workhorse device at the high end. FinFETs have scaled down to 3nm. What’s happening here?

Samavedam: FinFETs have been the workhorse device for five generations now, starting at 14nm. We’ve seen it at 14nm, 10nm, 7nm and 5nm as foundry offerings. Intel did introduce finFETs at 22nm. 3nm is also going to be a finFET node, at least for TSMC. If you want logic scaling, you have to scale the standard cell libraries. As you scale the standard cell library going from a 7.5-track to a 6-track or to a 5-track, the active device width that is available to build the finFET is reducing. So you go from three fins at 7.5-track to two fins at 6-track to a single fin device at 5-track. Single fin devices are more variable. This is one of the reasons why finFETs will stop scaling.

SE: 3nm appears to be the last node for finFETs. We are beginning to see a transition to nanosheet FETs, which is a gate-all-around (GAA) architecture. What benefits does that provide?

Fig. 1: Roadmap for transistors (top image) and interconnect technologies (bottom image). Source: Imec

Samavedam: If you replace the single fin with a stack of nanosheets, you can get more device width per footprint, and you can get more drive current per footprint. That’s the reason why you’re seeing the transition from finFETs to nanosheets. With nanosheets, you can build high-performance 5-track libraries. Nanosheets are also a gate-all-around device. If you surround the channel with a gate, you get much better gate control, which allows you to scale gate length a little more compared to finFETs. FinFETs are trigate devices. They have a gate on three sides of the channel, not all four sides. FinFETs have been scaling, going from 14nm down to 3nm, by scaling the fin pitch. You can get more fins per footprint by scaling fin pitch, and you can also scale the fin height to get more device width. Beyond 3nm, you’re hitting the limits of how tall fins can go. As the fins get taller, you can increase the drive current, but there is also a capacitance penalty. If the drive current increase cannot offset the capacitance penalty, it does not make sense to keep scaling the fin height. Also, as you take make finFET structures taller and the space between the fins is shrinking due to fin pitch scaling, it is more challenging to get the gate dielectric and the metal layers wrapped around the fins as you were able to do at relaxed dimensions. So finFET scaling is becoming more challenging, and nanosheets give you a way to get more drive current in the same footprint.

SE: What are the other benefits with nanosheet FETs?

Samavedam: Let’s look at finFETs. If you want to increase the device width, you have to go from one fin to two fins to three fins. It’s discrete. In nanosheets, you’re stacking nanosheets in an active area. You can vary the widths of the nanosheet and get different device widths. That gives you flexibility in designs. If you want transistors or standard cell libraries with higher and better drive current, you go with a wider sheet. If you want to optimize for capacitance and power, you can go with a narrow sheet. This is an added flexibility that nanosheets provide for designs.

SE: What are the manufacturing challenges with nanosheets?

Samavedam: The way you form these nanosheets is you first deposit multiple layers of silicon and silicon germanium using epitaxy. Then, you etch out the silicon germanium layers to get the silicon nanosheets. Growing the epi layers is reasonably well understood, but releasing these nanosheets is a challenge. You have to make sure that the silicon germanium etch is selective to silicon. It can’t roughen up the silicon channels that are left behind. You want to make sure they don’t stick together. As you etch away the silicon germanium, especially if you’re using wet etch, you want to make sure that there’s no stiction between the sheets.

SE: What are the other challenges?

Samavedam: The other challenge is more of a performance challenge. In finFETs, the majority of the current conduction is happening along the (110) surface. The sidewall of the fin is (110). That’s a good plane for PMOS mobility. Nanosheets are flat. They follow the same orientation as the substrate, so it’s a (100) orientation. PMOS takes a hit in drive current performance in the (100) orientation. To regain the performance in the PMOS, you have to stress these channels in the nanosheets. Incorporating stress into the nanosheet is a challenge. Forming multi-Vt devices is another challenge. The way you set the threshold voltage is to change the gate workfunction. So you incorporate different metal layers between the nanosheets to get different threshold voltages. The spacing between the nanosheets is tight. You need to etch one layer away and deposit a second layer to get a second workfunction material for a different threshold voltage. That’s quite challenging.

SE: Are the fab tools ready for nanosheets?

Samavedam: People have been working on gate-all-around structures for a few years now. The tools have come a long way in being able to support the unit processes for nanosheets. There are some challenges in metrology. In the nanosheet device formation, you have a module called the inner spacer, where you’re trying to separate the gate from the source/drain. You have to selectively etch the silicon germanium layer and then you fill it with a dielectric and form a spacer. That’s a challenging module from a metrology perspective. Controlling the lateral silicon germanium recess and forming the inner spacer, and then making sure that everything works, is challenging. People use scatterometry or optical CD to measure these structures. Sometimes, you may need to combine metrology techniques to get a good handle on the process control. But in general, the tools are available. Selective etch of silicon germanium relative to silicon is an important module. The tool wasn’t available in the beginning. Now it’s fairly well known how to do that.

SE: In nanosheets, EUV lithography will pattern the sheets. Any challenges here?

Samavedam: You will have to use single-print EUV, depending on the pitches you pattern. Purely from a lithography perspective, there may not be too many challenges there since EUV lithography is mature now. Nanosheet etch may still be a challenge since there are multiple layers to pattern.

SE: In advanced transistors, there are some major challenges with backend-of-the-line (BEOL), where the interconnects are made, right?

Samavedam: Our view is that copper dual damascene will scale down to about a 21nm pitch. But the challenge the industry faces is in via resistance. As you scale down the pitches, the via resistance is one that takes off. We’ve been looking at ways to mitigate the via resistance. You can do it a couple of different ways. You can selectively deposit different materials like ruthenium, molybdenum or tungsten, for example, so that you have a different via material with copper lines. Another way is to scale the liner/barrier material so that there is more room for copper in the vias. You can do it that way down to a 21nm pitch. If you want to scale below 21nm, we believe you have to go to direct metal etch. That’s what we refer to as semi-damascene integration. Some people also refer to this as subtractive metallization. You define the lines by direct metal etch. You can form high-aspect ratio lines, so that you can get low resistance lines. But when you go to high-aspect ratio lines, the capacitance is a problem, because you have a lot of overlap area between the two lines. To mitigate that, we plan to introduce air gaps to reduce the capacitance. If you want to do a direct metal etch in the semi-damascene integration, you have to go with metals that can be easily etched. Copper is not one of them. That’s why we chose ruthenium. Ruthenium is easier to etch compared to copper, and also it has a low resistance as you scale the linewidth.

SE: How far will we be able to scale the nanosheet? Where does Imec’s forksheet FET technology come into play?

Samavedam: The forksheet FET is an Imec innovation. As you continue to scale track height, you’re reducing the active width that is available for the device and the drive strength of the standard cells. This is why nanosheets are preferred over finFETs as track height is scaled. But even nanosheets will run out of steam as you try to scale track height further. You can scale the n-to-p space between the NMOS device and the PMOS device in the standard cell to create more active device width. You can scale that space by etching and forming a narrow dielectric wall. And that’s how the forksheet device comes about. It gives you more active width in the same footprint compared to the nanosheet, and it also has lower parasitic capacitance, which results in about a 10% performance benefit over nanosheets. It uses a lot of the integration infrastructure that we have already set up with nanosheets. It’s a way to extend the nanosheets by maybe one more generation. Between nanosheets and forksheets, we believe there’ll be about three more generations. So we will have 2nm and 14 angstrom, and likely 10 angstrom nodes with nanosheets and forksheets.

Fig. 2: Imec’s forksheet FET.

SE: Where does packaging and chiplets fit here?

Samavedam: There are many high-performance systems today that use 2.5D or 3D integration. In some cases, companies take an SoC and partition it into different functions, such as logic, memory, and I/Os. Each of those functions are built using different chiplets. Sometimes, they use different CMOS technologies. They put them together using different 3D interconnect technologies like interposers, die-to-wafer microbump bonding, or die-to-wafer hybrid bonding. We refer to this as the chiplet approach. That’s happening in high-performance, and eventually it will trickle down to mobile applications.

SE: Where is all that heading?

Samavedam: The approach the industry is following today is the chiplet approach. Each chip is designed separately and packaged together. What we envision is a true 3D SoC, where the logic and the memory die are co-designed. To do that, you need new EDA tool capabilities. In a true 3D SoC design, the place-and-route and timing closure can happen concurrently in both chips. Today, in the chiplet approach, you need a bus to connect the chiplets. That adds latency between the blocks, and it’s not very efficient. If you’re able to co-design the chiplets, and you’re able to do place-and-route and timing closure as a single SoC, you get a much more efficient compact design. You can avoid redundant buffers, and don’t have to worry about latency between these two blocks as you do in the current chiplet approach. We’ve been working with Cadence. They came up with a tool flow that enables you to do a true SoC 3D co-design between the chiplets. We will see more examples of this approach. The 3D SoC approach will take time, because the EDA tools are just being enabled.

SE: Another enabler for 3D packages and 3D SoCs is to scale the bump pitches, right?

Samavedam: We have demonstrated microbumps in research going down to 10μm, or even 7μm pitches. But if you look at the microbumps in production, they’re saturated at around 30μm pitches or so. If there’s enough push from the system companies to scale the interconnect densities, then you’ll see more offerings from the OSATs. To enable these tight microbump pitches, the equipment ecosystem needs to mature a little bit. We are partnering with equipment suppliers to do that. Once the EDA tools are enabled, the system companies will start to push for denser interconnects. Then, you will start seeing more of an offering for dense interconnects from the OSATs.

SE: How about hybrid bonding?

Samavedam: Today, there are several examples of hybrid bonding in production. Image sensor products use this. YMTC used hybrid bonding for connecting periphery logic and memory in 3D NAND. It’s a wafer-level technology today. You need clean CMP surfaces to achieve good hybrid bonds. If you do it at the wafer-level, the sizes of the top die and bottom die need to match. That’s one of the constraints. If it’s a wafer-level process, fabs are more likely to offer this technology than the OSATs. There are examples of die-to-wafer hybrid bonding. There is an example from AMD and TSMC, which was announced recently. So that’s an example of hybrid bonding at the die-to-wafer level.

SE: What are the challenges with hybrid bonding?

Samavedam: You need extreme planarity. That’s a constraint. To ensure a good hybrid bond, you need a dielectric that is compatible with copper. We use copper and SiCN as the dielectric. SiCN is a low-temperature deposited dielectric. That gives us the best bonding performance. Preparing the copper SiCN surface for hybrid bonding is still a bit of an art. There are many process optimizations needed in CMP. You have to use multiple CMP steps. You need very good local planarity, as well as global planarity, especially if you’re doing it at a wafer level. CMP control and having the right dielectric for hybrid bonding are the two key requirements.

SE: How do you define a 3D SoC?

Samavedam: You can partition the different functions in a 2D SoC like memory and logic, and design them separately. That’s the chiplet approach. What I mean by a 3D SoC is that you co-design the memory and the logic die as a single SoC. The connectivity can be at a much denser level, and you don’t have to worry about additional communication overhead between the two chips. It’s direct communication. You don’t need additional IP, a PHY, or a communication bus between the two chiplets. You can achieve more fine-grained partitions in 3D SoCs. To do that, you need denser interconnects. You also need the EDA tools to support this kind of a co-design.

SE: Will we ever see CFETs or devices with 2D materials?

Samavedam: 2D materials are promising because they offer high mobilities. They can form very thin atomic channels, so you can scale the gate length more aggressively. But there are also several fundamental materials issues that you have to address. You have to improve the mobility of the channel and contact resistance in the source-drain regions. We don’t know how to scale the gate dielectric thickness very well on these 2D materials. The way we build these devices may be quite different. There’s a lot of questions to be answered in the coming years to know whether these materials are real enough to make it to the roadmap.

SE: What about CFETs?

Samavedam: With CFETs, which stands for complementary FETs, the N and P devices are built on top of each other. Imec has demonstrated the concept of CFETs in the last couple of years. Intel has had a couple of papers in 2019 and 2020, as well. The challenge with CFETs is the integration. The integration is complex, and there are different ways of forming CFETs. You can do it in a monolithic fashion, where you’re forming the top active area and the bottom active area in the same step, and using a common self-aligned gate to connect the two devices. The challenge here is the need for many new complex unit processes, like high-aspect ratio patterning, high-aspect ratio depositions, etc. Or you can do it in a sequential fashion. In this approach, you build one device and bond a different wafer to process the next device. You can use a different substrate orientation or a different channel material for the top device. Here, the challenge is to connect the top gate to the bottom gate, because they are not self-aligned. One also needs to worry about the impact of the thermal budget of the top device on the bottom device. Void-free bonding between the top and bottom wafer with a thin dielectric in between is also very challenging since there are no good tools to detect these micro-voids. This is the complexity in sequential CFET integration. We are working on both schemes. From a device performance point of view, we believe they can be very similar. We can optimize the architectures for them to have similar performances, but the integration complexity is different in each of them. So that’s what we are trying to tackle right now.

Fig. 3: CFET in action. Source: Imec

SE: Traditional logic scaling and packaging/chiplets are more or less parallel paths, right?

Samavedam: They will happen in parallel. There are some components of the SoC that are not scaling very well. The I/Os or SRAMs, for example, don’t scale as well with logic nodes. So they could be manufactured with the more mature nodes and partitioned using the chiplet approach in a cost-effective way. Partitioning of SoCs into logic and memory is another way to increase the memory bandwidth to improve overall system performance. The chiplet approach and the 3D SoC approach are parallel tracks to conventional logic scaling.

SE: Where is all this heading?

Samavedam: I don’t see innovations in devices and materials, or density scaling, slowing down. We know high-NA (0.55) EUV is coming. That will enable denser patterns in a more cost-effective way compared today’s EUV at 0.33 NA. Scaling, as well as device architecture innovations, will continue. The chiplet approach or the 3D SoC approach is something that will happen in parallel to enable future systems scaling. They will all co-exist.

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Jan Hoppe says:

Lots of information. Some clarity on TSMC 3 nm.
Good true pics of transistors. Thanks for Excellency yes in information.
As for little me I see that sub nm precision of my in design 3D imaging and chemical analysis is to serve the right direction, thanks Semiconductor Engineering and Imec.
PS. GAA is so confined. Heat removal to be solved.

TanjB says:

Fork sheets only have three sides gated, compared to gate-all-around nanosheets. So, why are fork sheets regarded as an advance? They seem to be just finFETs turned sideways.

guest says:

What’s the nanosheet pitch? It’s loose than fin pitch, right? It may not need high NA.

Mark D LaPedus says:

Samsung has not publicly disclosed the pitches with its nanosheet FETs, which are due out in 2022. I believe the plan is to pattern the first nanosheets using today’s 0.33 NA EUV litho. I think you can do it using 193nm SADP/QP. Samsung hasn’t talked about that either way. Even so, today’s 0.33 EUV is required for the BEOL for the first nanosheets. High-NA EUV is slated for HVM in 2025. By then, it’s hard to predict what will happen.

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