Chiplets, Faster Interconnects, More Efficiency


Big chipmakers are turning to architectural improvements such as chiplets, faster throughput both on-chip and off-chip, and concentrating more work per operation or cycle, in order to ramp up processing speeds and efficiency. Taken as a whole, this represents a significant shift in direction for the major chip companies. All of them are wrestling with massive increases in processing demands ... » read more

Speed Returns As The Key Metric


For the foreseeable future, it's all about performance. For the past decade or so, power and battery life have been the defining characteristics of chip design. Performance was second to those. This was particularly important in smart phones and wearable devices, where time between charges was a key selling point. In fact, power-hungry processors killed the first round of smart watches. But ... » read more

Adaptation In A Volatile Era


2018 has been a volatile year by almost any measure, and the global electronics industry was at the center of the action. Soaring memory prices and tech stock valuations drove eye-popping growth in the first half, with Samsung solidifying its position as the world’s largest chipmaker and Apple briefly topping $1 trillion of market capitalization. Fast forward to the second half of the year an... » read more

Hybrid Memory


Gary Bronner, senior vice president of Rambus Labs, talks about the future of DRAM scaling, why one type of memory won’t solve all needs, and what the pros and cons are of different memories. https://youtu.be/R0hhDx2Fb7Q » read more

More Performance At The Edge


Shrinking features has been a relatively inexpensive way to improve performance and, at least for the past few decades, to lower power. While device scaling will continue all the way to 3nm and maybe even further, it will happen at a slower pace. Alongside of that scaling, though, there are different approaches on tap to ratchet up performance even with chips developed at older nodes. This i... » read more

Multiphysics Challenges For EDA Tools


Cost and performance are the main drivers for scaling of integrated circuits. However, some applications do not scale as easily as others. This is particularly true for analog circuits and everything related to high voltage and high power. Still, the demand for these kind of applications is growing rapidly due to new emerging markets such as Industry 4.0, IoT, and e-mobility. In the automoti... » read more

Is Advanced Packaging The Next SoC?


Device scaling appears to be possible down to 1.2nm, and maybe even beyond that. What isn't obvious is when scaling will reach that node, how many companies will actually use it, or even what chips will look like when foundries actually start turning out these devices using multi-patterning with high-NA EUV and dielectrics with single-digit numbers of atoms. There are two big changes playing... » read more

Going Vertical?


The topic of transistor scaling has been traditionally covered at SEMICON West in its own right. This year’s event, however, will also explore scaling in 3D, as well as using packaging to accomplish similar objectives. Along with traditional transistor scaling, speakers will tackle design and metrology considerations for scaling the package, and address the economic decisions that inform dens... » read more

Inside Next-Gen Transistors


David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation. SE: In a recent roundtable discussion you talked about some of the big challenges facing the IC industry. One of your big concerns involves th... » read more

Changing Direction In Chip Design


Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

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