Changing Direction In Chip Design

Andrzej Strojwas, chief technologist at PDF Solutions and professor of electrical and computer engineering at Carnegie Mellon University—and the winner of this year's Phil Kaufman Award for distinguished contributions to EDA—sat down with Semiconductor Engineering to talk about device scaling, why the semiconductor industry will begin to fragment around new architectures and packaging, and ... » read more

Moore’s Law Debate Continues

Does shrinking devices still make sense from a cost and performance perspective? The answer isn’t so simple anymore. Still, the discussion as to whether semiconductors are still on track with [getkc id="74" comment="Moore's Law"] occurs on a frequent enough basis to continue analyzing at least some of the dynamics at play. There is much speculation about what happens after 7nm, as well as ... » read more

Deeper Inside Intel

Mark Bohr, senior fellow and director of process architecture and integration at Intel, and Zane Ball, vice president in the Technology and Manufacturing Group at Intel and co-general manager of Intel Custom Foundry, sat down with Semiconductor Engineering to discuss the future directions of transistors, process technology, the foundry business and packaging. What follows are excerpts of those ... » read more

How To Scale IoT For “Time To Money,” Security

When it comes to design, IoT can be boiled down to “time to money.” It’s more complex than that, of course, but the unique, dynamic nature of the segment is changing the way we design systems and how we think about security. “IoT is not a device. It’s delivering service across the cloud to connected devices,” said Nandan Nayampally, vice president of marketing with ARM. “In the... » read more

RC Delay: Bottleneck To Scaling

R = resistance — the difficulty an electrical current has in passing through a conducting material. C = capacitance — the degree to which an insulating material holds a charge. RC delay = the delay in signal speed through the circuit wiring as a result of these two effects. RC delay is important because it can become a significant obstacle to continued downward scaling of logic and... » read more

No More Straight Lines

Shrinking features on a chip is no longer the only way forward, and in an increasing number of designs and markets, it is no longer the best way forward. Power and performance are generally better dealt with using different architectures and microarchitectures, and all of those provide the potential to reduce silicon area (cost). Cramming more transistors on a die and working around leakage... » read more

The Economics Of Moore’s Law

By Marc Heyns I’m very optimistic about the continuation of Moore’s Law. But in saying that, I’m speaking about Moore’s Law purely as an economic law. I believe we’ll be able to offer increasing amounts of functionality at lower and lower costs. And technological innovations as well as advances in design and application will be crucial in realizing this. But I don’t believe a ne... » read more

Executive Insight: Aart de Geus

SE: What worries you most? De Geus: Everything I do is with high intensity, and what is of super high intensity right now—and there are challenges and opportunities in it—is that we have the confluence of some very big changes right now happening at the same time. On the technology side, there are multiple intersections. One is the intersection of another 10 years of Moore’s Law—finF... » read more

Looking Beyond Moore’s Law

For decades, chip scaling has followed a simple linear curve. In this curve, the transistor gate-pitch scales at 0.7x every two years. This is the driving force behind Moore’s Law, which states that the number of transistors per chip roughly doubles every two years. But starting at the 16nm/14nm node, there is a change taking place in chip scaling. According to a chart from Imec, there are... » read more

Speeding Up NMOS

By Ed Sperling For years—decades, in fact—the NMOS transistor world has been on cruise control. NMOS is naturally faster and its performance has scaled better than PMOS. PMOS has had a cost advantage. But lately, it has been catching up in performance, too. In fact, at 20nm the two transistor types have proven nearly equal in performance—but not for long. NMOS is about to get a big bo... » read more

Newer posts →