Bumps Vs. Hybrid Bonding For Advanced Packaging

New interconnects offer speed improvements, but tradeoffs include higher cost, complexity, and new manufacturing challenges.


Advanced packaging continues to gain steam, but now customers must decide whether to design their next high-end packages using existing interconnect schemes or move to a next-generation, higher-density technology called copper hybrid bonding.

The decision is far from simple, and in some cases both technologies may be used. Each technology adds new capabilities in next-generation advanced packages but it comes with its own set of tradeoffs and challenges.

For years, the industry has used traditional copper microbumps as the interconnect scheme for many midrange to high-end packages. Tiny copper bumps are formed on dies and then connected and assembled into a package, providing small, fast electrical connections between devices. The most advanced microbumps use a 40μm pitch, which involves a 25μm bump size with 15μm spacing between the adjacent bumps on the die. Going forward, bumps can be scaled down to 20μm or 10μm pitches, but this adds other challenges.

Microbumps may hit the wall at 10μm pitches, prompting the need for a new technology called copper hybrid bonding. Targeted for 10μm pitches and below, hybrid bonding connects dies in packages using tiny copper-to-copper connections, as opposed to bumps. It provides more interconnect density, enabling 3D-like packages and advanced memory cubes. But hybrid bonding also adds some challenges in the fab.

Still, after years of R&D, hybrid bonding is nearly ready at some vendors. Some aren’t waiting until copper bumps hit the wall. Instead, they’re planning to deploy hybrid bonding ahead of the competition.

“Several logic and memory customers are in various stages of deploying hybrid bonding solutions,” said Manish Ranjan, managing director of the advanced packaging business segment at Lam Research. “One of the key challenges is to come up with cost-effective integration schemes, especially for applications requiring lower temperature bonding and improved alignment accuracy during the bonding process. From a plating perspective, we believe that grain engineering will become important for enabling next-generation hybrid bonding solutions.”

By year’s end, for example, AMD plans to introduce 3D V-Cache, an SRAM-based cache device stacked on a processor using hybrid bonding. This is being manufactured by AMD’s foundry partner, TSMC, which has aggressive plans for hybrid bonding.

But not all are moving to hybrid bonding initially. For example, Intel plans to extend bumps and will migrate to hybrid bonding later. GlobalFoundries, Imec, Leti, Samsung, UMC, Xperi, and others are working on the technology. As it turns out, the industry needs both microbumps and copper hybrid bonding. Each technology has its place. But to be sure, a large percentage of packages don’t require advanced interconnects.

Nonetheless, next-generation interconnects are important for more reasons than just connecting dies. They propel the development of more advanced packages, as well as the chiplet model. For chiplets, a chipmaker may have a menu of modular dies in a library. Customers then can mix-and-match the chiplets and integrate them in existing advanced packages or new architectures.

All of this, in turn, could reshape the chip design and manufacturing landscape. Traditionally, to advance a chip design, vendors would develop a system-on-a-chip (SoC). At each generation, vendors crammed more functions on the SoC. But this is becoming more difficult and expensive at each new node. So while this method remains an option for new designs, the industry is searching for alternatives. Another way to get the benefits of scaling is by putting complex chips in advanced packages, increasingly relying on heterogeneous integration.

Chiplets, a form of heterogenous integration, promise to enable new architectures that mimic today’s SoC, but are developed at lower costs. “We are going to see more of that. You will see an increasing number of chiplet designs next year,” said Jan Vardaman, president of TechSearch International.

Fig. 1: AMD’s 3D V-Cache stacks the cache on a processor. Source: AMD

End of Moore’s Law?
For decades, the IC industry has attempted to keep pace with Moore’s Law, doubling the transistor density in chips every 18 to 24 months. But starting a decade ago, at 20nm, chipmakers began replacing planar transistors with finFETs because the gate structure on smaller transistors was insufficient to control current leakage. Transistors continued to leak after devices were turned off, which continued to drain batteries.

Intel introduced finFETs at 22nm in 2011, using what it called a Tri-Gate structure to control leakage at three points in the “off” state, and allow more current to move through when the vertical gates were opened in the “on” state. Foundries followed with finFETs at 16/14nm.

But finFETs also are more complex, driving up design and manufacturing costs. The cost to design a 7nm device is roughly $217 million, compared to $40 million for a 28nm chip, according to Handel Jones, CEO of IBS.

For chips at 7nm and below, the power and performance benefits have started to diminish, leaving many to realize that developing an SoC isn’t always the right solution. “A monolithic die approach forces a one-size-fits-all solution, which is not optimal,” said Walter Ng, vice president of business development for UMC.

So the industry is looking at alternatives, such as advanced packaging, which promises to address several issues in systems. For example, vendors can break up a large SoC into smaller chiplets and incorporate them in a package, creating an advanced system-level design. “Therefore, the system can be optimized by using the best processor components with an optimum performance/cost process node,” said Xiao Liu, senior program manager from Brewer Science, in a paper at the IEEE Electronic Components and Technology Conference (ECTC).

For this and other applications, there are several ways to integrate chips in packages, such as fan-out. In one example of fan-out, a DRAM die is stacked on a logic die in a package.

2.5D is another option. In 2.5D, dies are stacked on an interposer, which incorporates through-silicon vias (TSVs). Another option is 3D-ICs, where logic-on-logic or logic-on-memory are stacked in a 3D-like package.

None of these technologies will replace traditional SoCs, but they can be used to supplement them. In fact, leading-edge chips often are incorporated in advanced packages. The package boosts the performance of the design.

Going forward, there is some uncertainty. Chipmakers are ramping up 5nm chips, with 3nm and beyond in R&D. It’s hard to predict when, but at some point traditional chip scaling will falter. When that occurs, the industry will need help from packaging to stay on the roadmap. That’s why the chiplet model is important. In one futuristic scenario, vendors may integrate chiplets in 3D-like packages, creating system-level designs that mimic a traditional SoC.

Nonetheless, there are many packaging options today with bumps and other interconnect schemes. Now, hybrid bonding is in the mix. So what’s the best option?

Do the bump
Today, a number of different entities develop packages — IDMs, foundries, OSATs, and R&D organizations. IDMs make and sell their own chips, and some suppliers also have their own internal packaging operations. Foundries manufacture chips for others, and some vendors provide packaging services for customers. OSATs provide packaging services for third parties.

For decades, the semiconductor industry has used wire bonding to create packages. In a wire bonder, a chip is stitched to a package using tiny wires. Today, some 75% to 80% of packages are assembled using wire bonding, according to TechSearch.

Wirebonding, however, doesn’t provide enough I/Os for processors and other chips. “I/Os refer to the connections that take the signals and/or power and ground connections either into the package or out of the package,” explained John Hunt, senior director of engineering at ASE.

So back in the 1960s, the industry developed flip-chip technology to boost the I/O counts in packages. Flip-chip is an interconnect scheme, providing connections from one die to another die or a die to a board.

Flip-chip is used to make various package types. Originally, in a flip-chip flow, tiny solder balls are formed on top of the chip. The device is flipped and mounted on a separate die or board. The die or board consists of pads. The solder balls land on the pads, forming electrical connections.

Solder balls are 75µm to 200µm in diameter. While they are still used today, that use is limited because of the size. Starting at 65nm in 2005, Intel and others moved to copper microbumps. In the flow, microbumps are formed on the dies. Using the same flip-chip process, bumped dies are connected and assembled into packages. Copper microbumps enable more I/Os with smaller pitches and better thermal conductivity than solder bumps, which is why they have become the mainstream interconnect technology for many midrange and high-end packages.

At the high end, high-bandwidth memory (HBM) is one example. Used in advanced packages, HBM stacks DRAM dies and connects them with bumps at 40μm pitches. HBMs provide more memory bandwidth in systems.

In another example, Intel recently introduced a 3D CPU platform, combining a 10nm processor core with four 22nm processor cores in a package. Devices are stacked using 36μm bump pitches.

Copper bumps consist of a copper pillar with a solder cap, based on a tin/silver alloy. To make copper bumps, a surface is deposited with an under-bump metallurgy (UBM). Then, a photoresist is applied on the UBM. The desired bump size is patterned and etched, forming a small gap in the resist. A copper layer is plated over the surface, forming a pillar in the gap. In some cases, this material is reflowed or heated, forming the bump.

To stack and connect bumped dies in packages, the industry uses thermal compression bonding (TCB). In operation, a TCB bonder picks up a die and aligns the bumps to those from another die, then bonds the bumps using force and heat. TCB, however, is a slow process.

Beyond 40μm pitches, the big question is whether it makes sense to develop next-generation packages with finer-pitch bumps or deploy hybrid bonding. The answer depends on the product and application. Next-generation bumps and hybrid bonding are too expensive and not required for most apps.

“The demand is driven by cost. The finer the pitch, the more expensive the process,” said Annette Teng, CTO of Promex. “We’re still seeing coarse-pitch packages at 140μm to 150μm. That’s still mainstream, and it’s not going to change anytime soon. We are starting to see some 110μm to 120μm, but 40μm and below is still at the R&D level. That requires a whole new set of masks and technology, so we don’t think it will become mainstream in the immediate future.”

Nonetheless, several IDMs, foundries, and OSATs are capable of developing bump pitches beyond 40μm. They can leverage the existing processes to develop finer-pitch packages. But not all companies are capable of hybrid bonding. This requires a fab with expensive equipment.

From a technology point of view, there is a clear delineation between using microbumps or hybrid bonding. Microbumps are viable with about 10 to 20µm pitches and above, while hybrid bonding is 10µm and below.

A case can be made for extending the existing the bump pitches in high-end packages beyond 40µm. “With the growing demand for heterogenous integration with silicon-to-silicon 3D packaging, there is great interest to reduce the die-to-die interconnect pitch, as the smaller pitch enables simpler and more efficient circuits, resulting in lower power consumption and a reduction in design complexity,” said Zhaozhi Li, an engineer from Intel, at ECTC.

Work is already underway here. “Next year, we have a couple of customers moving towards the development of 35µm pitch in 2022 with products in 2024 to 2025,” said Mike Kelly, vice president of advanced packaging development and integration at Amkor. “For mainstream compute, 35µm will become common in the 2025/2026 timeframe.”

Packaging houses have demonstrated 20µm and 10µm bump pitches, but there are some major challenges. In packages, the microbumps must be uniform. If there is variation in the structures, the package may encounter some reliability issues.

At finer pitches, though, the bumps are smaller with less solder material. At 40μm pitches, the bump sizes are 25μm. At 20μm pitches, they are less than 10μm. During the process, problems are likely to occur with smaller bumps and the solder joints, such as cracks and voids.

“The main challenges of this fine microbump interconnections come with bump coplanarity,” said Mu Hsuan Chan, a technical manager from Siliconware, part of ASE, in a presentation at ECTC. “Owing to finer solder volume on a much finer microbump pitch, solder is rapidly consumed after solder joint formation, and voids could form. The voids within the solder joint will deteriorate the solder joint reliability of the bumps.”

Intel explored ways to enable microbumps at 20μm and 10μm pitches, reporting its findings in a study. The company devised test chips with bumps. Then, it analyzed the placement accuracy specifications for various TCB tools. The best tool could place 99.9% of the dies with alignment accuracy better than 2.1μm.

TCB tools are capable of 20μm pitches, but it’s a different story with 10μm. Using TCB with good accuracy, the process caused faulty solder joints, according to Intel.

Intel and others are looking for ways to extend the bump to 10μm, including the use of new diffusion barrier metals. These would reside between the copper bump and solder. There are some promising candidates. Even then, however, many challenges and unknowns remain.

Hybrid bonding approach
At about 10μm and below, the industry will need copper hybrid bonding, and some will jump to hybrid bonding even before bumps reach their limits.

Hybrid bonding isn’t new. Starting in 2016, Sony began shipping CMOS image sensors using this technology. Smartphones incorporate cameras, each of which is powered by an image sensor.

For image sensors, a vendor develops a logic wafer in a fab. Then, the vendor processes a separate wafer with an image sensor. Using a wafer bonder, the two wafers are bonded using fine-pitch copper-to-copper interconnects. It’s a dielectric-to-dielectric bond, followed by a metal-to-metal connection. The individual chips are diced on the wafer, forming image sensors.

Hybrid bonding works the same way in packaging, but it’s more difficult. That’s why hybrid bonding for packaging has been stuck in R&D for years.

That’s about to change. The industry is working on three copper hybrid bonding flows, including wafer-to-wafer, die-to-wafer, and die-to-die. Wafer-to-wafer involves stacking and bonding two wafers, die-to-wafer stacks a die on a wafer, and so on.

Hybrid bonding enables an assortment of possible chip architectures, mainly for high-end applications. “In addition to AI, we also see HPC, GPUs, mining processors, gaming processors, as well as image sensors using hybrid bonding,” said Michael Wang, assistant vice president of corporate marketing at UMC.

Today, several entities are working on hybrid bonding. At ECTC, vendors presented papers on the following technologies:

  • A*STAR devised a 10 x 10mm test chip with a 12µm pad pitch.
  • Fraunhofer demonstrated a 10μm hybrid bonding flow.
  • Imec devised a stacked face-to-face and back-to-back flow.
  • Intel taped out test chips, including a 10nm finFET.
  • Leti devised a path towards 5μm pitches with hybrid bonding.
  • Samsung demonstrated 3-stacked wafer bonding using hybrid bonding.
  • UMC showed a pre-bond qualification process for TSVs.

AMD is one of the early adopters here. AMD recently disclosed the development of a 64MB SRAM, which is stacked and bonded on a Ryzen 5000 processor using hybrid bonding. Both devices are based on TSMC’s 7nm process. This device is slated to ship by year’s end.

AMD’s 3D V-Cache triples “the amount of high-speed L3 cache feeding our Zen 3 cores. [It supports] more than 2 terabytes per second of bandwidth,” said Lisa Su, CEO of AMD, in a recent presentation. It’s a potential game changer. Hybrid bonding provides 15 times more interconnect density and 3 times the energy efficiency than microbumps, Su said.

TSMC, AMD’s foundry partner, has been working on hybrid bonding for some time. TSMC calls this System on Integrated Chip (SoIC), which enables new, chiplet-like architectures.

Others are developing products around SoIC.

“The trend we are seeing is that more and more customers want to figure out a way to integrate different pieces together. They want to mix-and-match different functional dies together,” said Kevin Zhang, senior vice president at TSMC. “The business model is not different than our wafer business. We work with customers to identify the right chiplets and integration schemes. When we stack different chips together, each chip comes from our customers. They are all customer-specific designed IP. They choose the fabric they want to integrate. We provide the solution to help customers to integrate different chiplets together with different advanced integration techniques. The IP we provide is foundational IP, like a standard library and SRAM memory compilers. Those serve as building blocks. When customers design a chiplet for a given application, they leverage our foundational IP. We partner with EDA vendors to build a common design platform, allowing customers to integrate different IPs together. At the chiplet level, the design is owned by the customer.”

UMC and other foundries are developing a similar business model. But it’s challenging to develop products using hybrid bonding. “The big challenges for hybrid bonding are wafer surface cleanliness, wafer warpage, and step height between the copper and dielectric materials in a die,” said Tony Lin, technology director at UMC.

This process starts in the fab, where the chips are processed on a wafer. Then the wafers undergo a single damascene process, forming the copper-to-copper interconnects. For this, an oxide material is deposited on a wafer. Tiny vias are patterned and etched in the oxide material. The vias are filled with copper using a deposition process. A second wafer undergoes the same process.

At this point, let’s say you are developing a chip product using a wafer-to-wafer process. Using Leti’s wafer-to-wafer flow, there are two copper damascene levels on each wafer. The top level consists of copper pads, while the bottom incorporates copper vias. Then, the copper pads on the wafers are polished using a chemical mechanical polishing (CMP) tool. Using a wafer bonder, the top wafer is flipped and bonded to the bottom wafer.

“The pitch of the copper pads defines the alignment specification. A good alignment capability is required to ensure the electrical contact through the bonding interface,” explained Emilie Bourjot, a 3D integration project manager at Leti. “Direct hybrid bonding refers to molecular bonding of two surfaces composed of copper interconnections within an SiO2 matrix. When these two surfaces are intimately in contact at room temperature, Van der Walls bonds create adhesion. Those bonds are then changed into covalent and metallic bonds after a thermal budget.”

Fig. 2: Wafer-to-wafer flow. Source: Leti

Fig. 3: Die-to-wafer flow. Source: Leti die-to-wafer hybrid bonding flows. Source: Leti

Die-to-wafer is more complex. In one example, SRAM dies are processed on a wafer. Using hybrid bonding, copper interconnects are formed on the dies. The dies are diced.

CPUs are processed on a separate wafer. Copper interconnects are formed on top. Using a bonder, the SRAM dies are flipped, stacked and bonded to each CPU.

In this flow, two wafers undergo a damascene process, followed by CMP. CMP is challenging. If the wafer is over-polished, some of the copper pads may not join during the bonding process. If under-polished, copper residue can create electrical shorts.

Then, several types of metrology systems characterize the surface topography. “Regarding 3D-ICs, we see more and more stringent metrology control,” said Samuel Lesko, senior manager for application development at Bruker. “The die flatness, the local recess on the pad, and the roughness on those pads are really critical.”

The chips in the top wafer are diced and placed in a holder. The bonding step is next. In operation, a flip-chip bonder will pick the die directly from a dicing frame or holder. Then, the system will place the die onto a host wafer or another die. The two structures are bonded at room temperature.

This isn’t a simple process. “The challenge is good accuracy (<1µm) with a system that is still able to provide good throughput. In the system, fast gantries introduce vibrations and have limited position accuracy,” said Birgit Brandstätter, funding manager of R&D at Besi. “Cleanliness is another big challenge. Hybrid bonding requires almost zero defects, while moving machine parts generate particles and disturb a linear flow of clean air. Thus, the machine design and materials must comply with cleanroom standards in addition to their critical functionality for the pick and place.”

Advanced packaging is an enabling technology with many options. Now, there are more interconnect options at the high end.

These options will enable more advanced packages, paving the way towards new designs that could reshape the semiconductor landscape.

Related Stories
Stronger, Better Bonding In Advanced Packaging
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Bonding Issues For Multi-Chip Packages
Disaggregation solves some problems, but it creates new ones.
The Darker Side Of Hybrid Bonding
The approach offers huge performance gains, but pitfalls remain.
Fan-Out Packaging Options Grow
Once viewed as a low-cost IC packaging option, fan-out is going mainstream and upstream.
Advanced Packaging’s Next Wave
A long list of options is propelling multi-chip packages to the forefront of design, while creating a dizzying number of options and tradeoffs


Hugo Pristauz says:

I enjoyed to read this nice summary, as I was an evangelist for Hybrid Bonding at Besi, and now the technology really grabs gain. While “Heterogeneous Integration” was 4 years ago an insider domain it’s now almost like coffeeshop talk. Gordon Moore emphasized that his law will end in 2025, so I’m very curious what this means in particular (it’s only 4 years from now). Interesting also that Intel seems to leave technology leadership to TSMC and AMD, they surely have their reasons, but what will be the consequences?

JT SUH says:

Hello Mark !

It is valuable and excellent investigation with well orgainxed summary.
thermal dissipation issue and reliability concern with cost reduction topics are left for cxxxy process engineers.
Thank you much!

Dr. Dev Gupta says:

I find it amusing that LETI chooses to define the almost day-long anneals needed for Hybrid bonding ( to develop Cu||Cu bonds by grain growth in the Cu bond pads ) as a mere thermal “budget”. They are finding out the hard way that Co Planarity ( rather lack thereof ) can be a yield killer for hard Cu – Cu bonds w/o the benefit of a Sn layer for compliance.

So it is discouraging to see so many Brute Force attempts at geometry shrinks of Flip Chip Bumps ( be they Sn coated or bare Cu ) w/o a fundamental understanding of the Metallurgy or even basic Physics.

But Foundries w/ deep pockets keep indulging in loss-leader type forays into new advanced packaging technologies — even when the technologies push unnecessary/immature technologies on their captive fabless customers and do not make sense, performance- or cost-wise. First it was FO WLPs, even for SoCs that require packages w/Fan Out Ratio > 2 (when FC on Coreless substrates as in the molded Mitsubishi FC package still used by QCOMM for their SoCs would have been a better choice ). This continues for the rest of their captive fabless customers ( e,g. AMD opting for Hybrid Bonding for their SRAM Cache stacked over a Processor). It will be interesting to track the yield (or AMD orders for the SRAM chips, which AMD has to procure from a vendor that is NOT the foundry.

Dr. Dev Gupta
Packaging IFT
IEEE IRDS International Semiconductor Devices Roadmap

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