中文 English

Week In Review: Semiconductor Manufacturing, Test


Imec released its semiconductor roadmap, which calls for doubling compute power every six months to handle the data explosion and new data-intensive problems. Imec named five walls (scaling, memory, power, sustainability, cost) that need to be dismantled. The roadmap (below) stretches from 7nm to 0.2nm (2 angstroms) by 2036, and includes four generations of gate-all-around FETs followed by thre... » read more

The Path To Known Good Interconnects


Chiplets and heterogenous integration (HI) provide a compelling way to continue delivering improvements in performance, power, area, and cost (PPAC) as Moore’s Law slows, but choosing the best way to connect these devices so they behave in consistent and predictable ways is becoming a challenge as the number of options continues to grow. More possibilities also bring more potential interac... » read more

Heterogeneous Integration: Fertile Ground For Medical And Biotech Innovation


Sensing components in medical and biotech devices often place severe restrictions on the assembly methods that can be employed, which is part of what is driving heightened demand for heterogeneous integration (HI). It is the newest frontier for the medical and biotech manufacturing services industry to contribute our own innovations by developing the processes to build these unique combinations... » read more

Hot Trends In Semiconductor Thermal Management


Increasing thermal challenges, as the industry moves into 3D packaging and continues to scale digital logic, are pushing the limits of R&D. The basic physics of having too much heat trapped in too small a space is leading to tangible problems, like consumer products that are too hot to hold. Far worse, however, is the loss of power and reliability, as overheated DRAM has to continually r... » read more

Heterogeneous Assembly


Medical and biotech devices often include optical, chemical, RF, and liquid elements. Some are combined with electronic devices to increase functionality or interaction with the environment. To produce these devices, multiple technologies are combined in a cost-effective way, ideally using a rapid process development cycle to minimize time to market. Combining technologies, as well as combining... » read more

Bump Co-Planarity And Inconsistencies Cause Yield, Reliability Issues


Bumps are a key component in many advanced packages, but at nanoscale levels making sure all those bumps have a consistent height is an increasing challenge. Without co-planarity, surfaces may not properly adhere. That can reduce yield if the problem is not identified in packaging, or it can cause reliability problems in the field. Identifying those issues requires a variety of process steps... » read more

Heterogeneous Integration Device Assembly: Key To Enabling Additional Innovations


Heterogeneous integration (HI) improves device functionality by expanding the types of parts and physical configurations combined with silicon chips. Different parts add new functions – with minimal additional volume – thus increasing overall functionality per unit volume. By comparison, classic methods employed to build electronic products, e.g., circuit boards or metal boxes, increase pro... » read more

Variation Making Trouble In Advanced Packages


Variation is becoming increasingly problematic as chip designs become more heterogeneous and targeted by application, making it difficult to identify the root cause of problems or predict what can go wrong and when. Concerns about variation traditionally have been confined to the most advanced nodes, where transistor density is highest and where manufacturing processes are still being fine-t... » read more

Week in Review: Manufacturing, Test


Industry Numbers NAND flash memory is forecast to hit US $83 billion this year, an increase of 24%. DRAM is projected to hit $118 billion, up 25%, according to a recent Yole report. Both are historic records. DRAM and NAND revenues are expected to be a $260 billion market in 2027 (combined), with advanced technologies such as EUV lithography, hybrid bonding and 3D DRAM driving this. SEMI in... » read more

Paving The Way To Chiplets


The packaging industry is putting pieces in place to broaden the adoption of chiplets beyond just a few chip vendors, setting the stage for next-generation 3D chip designs and packages. New chiplet standards, and a cost analysis tool for determining the feasibility of a given chiplet-based design, are two new and important pieces. Along with other efforts, the goal is to propel the chiplet m... » read more

← Older posts