The Darker Side Of Hybrid Bonding

The approach offers huge performance gains, but pitfalls remain.


With semiconductors, it’s often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance.

Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn’t easily translate for hybrid bonding, where pads are bigger and the copper recess requirement is more stringent. Existing bonders for flip chip assembly have an alignment accuracy of 3 microns or better. An industry rule of thumb estimates that bond pads need to be five times larger than the bonder’s accuracy to get adequate yield. A shallow and uniform copper recess is necessary for void-free bonding, but the CMP recess depth tends to increase with pad size. Scaling hybrid bonding below 3 microns will require improved CMP processes.

Among other things, the CMP process will need to be optimized for pattern density effects, in both the bond layer and underlying metal layers. Thomas Uhrmann, EV Group director of business development, noted that contact pads often are concentrated along the edges of the chip, while the rest of the chip area is blank. So to achieve uniform CMP performance, dummy pads may be needed. The underlying interconnect structures also may affect wafer shape and wafer stress.

Higher pad densities are more vulnerable to bonding voids regardless of pad size. Soon-Wook Kim and colleagues at Imec, in work presented at the 2020 IEEE Electronic Components and Technology Conference, explained that if an isolated pad protrudes, it can hold the nearby dielectric surfaces away from each other, thereby creating a void. If a pad in a dense array protrudes, though, adjacent voids can coalesce to create a larger gap.

It’s possible for the pad design to help compensate for alignment limitations. Eric Beyne, the director of Imec’s 3D System Integration Program, explained that one approach matches a small, slightly protruding copper pad on one wafer to a wider, slightly recessed copper pad on the other. The size difference depends on the overlay tolerance of the bonding system. This design ensures that a strong bond that does not overlap the dielectric can still occur, even if the smaller pad is not precisely centered on the destination wafer. Another solution, also demonstrated by Imec, uses short copper lines rather than square pads, with horizontal lines on one layer matching vertical lines on the next. Not only are the lines less prone to dishing, but a successful bond can occur even if overlay mismatch shifts the “center” of the line fairly substantially.

TEM hybrid Cu/SiCN to Cu/SiCN bonding. Top Cu pads are 270nm and bottom ones are 400nm with 700nm pitch. Source: Imec

Fig. 1: TEM hybrid Cu/SiCN to Cu/SiCN bonding. Top Cu pads are 270nm and bottom ones are 400nm with 700nm pitch. Source: Imec

To prevent voids and other defects, hybrid bonding requires a flat, clean contact surface. In wafer-to-wafer bonding, a well-controlled CMP process can be counted on to provide such a surface. After that, the Xperi group completes preparation of the destination wafer with a DI water rinse and plasma treatment. The company believes the risks of room temperature copper oxidation are overstated, and so aggressive cleaning steps to remove any oxide are not needed.

Xperi views oxidation at elevated temperature as a more serious concern. For that reason, it has focused on reducing the temperature requirements of their process, most recently reporting a 200°C anneal for 1 hour.

EV Group’s bonding process chamber is not designed for deposition or etch, Uhrmann said, but uses a relatively gentle plasma to modify the surface reactivity. When the initial dielectric adhesion step uses water to pull the surfaces together and facilitate bonding, for instance, surface treatments seek to create OH groups, modify subsurface bonding, and so on.

Singulated dies aren’t clean
While wafer-to-wafer bonding can usually count on a clean starting surface, hybrid bonding used as part of a heterogenous integration scheme is a different animal. Whether the process places singulated chips directly on the destination wafer, or on an interposer or temporary substrate, the challenges are similar.

In die-to-wafer (or interposer) bonding, singulation of the dies is a potentially huge source of particles and other contaminants, leading to voids and other defects at the bonding interface. All failures that the Xperi group found were due to particle-induced voids, not CMP-related defects like topography variation. Researchers at Imec are investigating plasma dicing, glass carrier, and alternative protective layers to improve defectivity.

Who pays for it all?
One of the most challenging issues with hybrid bonding is cost. That raises questions about where in the supply chain it actually fits.

Chip manufacturers, both foundries and IDMs, see this kind of processing as an extension of the wafer fab back end of line. Relative to other kinds of packaging, Beyne said that the equipment involved is more expensive and more automated, and process cleanliness requirements are much more stringent.

On the other hand, one of the key arguments for heterogenous integration is that integrated packages may include components sourced from multiple different companies. System integrators would rather not be overly dependent on a particular wafer fab. Foundries, meanwhile, would like fabricate both the integrated package and all of the component chips.

The tension between the two viewpoints opens a market opportunity for OSATs. Actually exploiting the opportunity is not so easy, though. Packaging historically has been a low-margin, low-value-add business. Heterogenous packages require more expensive processing, but add more value, too. To be financially viable, shops that make them need to capture some of that value for themselves. Without it, hybrid bonding is likely to remain the exclusive domain of large volume, single-manufacturer components.

Bonding Issues For Multi-Chip Packages
Disaggregation solves some problems, but it creates new ones.
Variation Threat In Advanced Nodes, Packages Grows
Complex interactions and tighter tolerances can impact performance, power and life expectancy.


Ed Korczynski says:

Excellent overview of IC Heterogeneous Integration (HI). Regarding die-cleanliness, remember that plasma-dicing and protective sacrificial coatings are proven “off-the-shelf” technologies… while the costs for such value-adding must be constrained. All of this leads to a fresh set of problems/opportunities for materials suppliers, OEMs, and OSATs!

Dr. Dev Gupta says:

Cu – Sn TCB Flip Chip Bonding of uPillar bumps ( 50 um pitch ) as used by offshore APAC houses is already a quarter century old process. It had been put into production 23 years ago by Motorola Semiconductor in AZ to do high volume assembly ( using a totally homegrown Robotic line w/ Flip Chip Bonders of proprietary design ) of Power Amplifier modules for Motorola Flip Phones using FC GaAs FETs ( w/ Bump Pitch of 25 um already ) that revolutionized Mobile Phones by allowing Bandwidths large enough to access the Net, while still keeping the packaging cost below previously Wire Bonded versions !

Not much fundamental improvements have been done to optimize this technology for stacked dies.
Once all this CoVid nonsense is brought under control, we will disclose the next generation of TCB optimized for Die Stacking, based once again on Theory, NOT incremental / superficial engineering.

Should extend the life of TC FCB by a few years till Hybrid FCB gets ready for HBM etc.

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