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Improving Redistribution Layers for Fan-out Packages And SiPs


Redistribution layers (RDLs) are used throughout advanced packaging schemes today including fan-out packages, fan-out chip on substrate approaches, fan-out package-on-package, silicon photonics, and 2.5D/3D integrated approaches. The industry is embracing a variety of fan-out packages especially because they deliver design flexibility, very small footprint, and cost-effective electrical connect... » read more

Revising 5G RF Calibration Procedures For RF IC Production Testing


Modern radio frequency (RF) components introduce many challenges to outsourced semiconductor assembly and test (OSAT) suppliers whose objective is to ensure products are assembled and tested to meet the product test specifications. The growing advancement and demand for RF products for cellphones, navigational instruments, global positioning systems, Wi-Fi, receiver/transmitter (Rx/Tx) componen... » read more

The Race To Zero Defects In Auto ICs


Assembly houses are fine-tuning their methodologies and processes for automotive ICs, optimizing everything from inspection and metrology to data management in order to prevent escapes and reduce the number of costly returns. Today, assembly defects account for between 12% and 15% of semiconductor customer returns in the automotive chip market. As component counts in vehicles climb from the ... » read more

Enablers And Barriers For Connecting Diverse Data


More data is being collected at every step of the manufacturing process, raising the possibility of combining data in new ways to solve engineering problems. But this is far from simple, and combining results is not always possible. The semiconductor industry’s thirst for data has created oceans of it from the manufacturing process. In addition, semiconductor designs large and small now ha... » read more

Current And Future Packaging Trends


Semiconductor Engineering sat down to discuss IC packaging technology trends and other topics with William Chen, a fellow at ASE; Michael Kelly, vice president of advanced packaging development and integration at Amkor; Richard Otte, president and CEO of Promex, the parent company of QP Technologies; Michael Liu, senior director of global technical marketing at JCET; and Thomas Uhrmann, directo... » read more

The Need For Open Molded Plastic Packages


When you need to meet a project or customer deadline, can you count on your outsourced semiconductor assembly and test (OSAT) provider to get you the parts when you need them? If the answer is “no” or “it depends,” you’ll understand the value of having open molded plastic packages – plastic packages with open cavities – readily available for quick-turn assembly. OSATs are v... » read more

Piecing Together Chiplets


Several companies are implementing the chiplet model as a means to develop next-generation 3D-like chip designs, but this methodology still has a long way to go before it becomes mainstream for the rest of the industry. It takes several pieces to bring up a 3D chip design using the chiplet model. A few large players have the pieces, though most are proprietary. Others are missing some key co... » read more

Rethinking Business As Usual


Few things can snap your priorities into focus like the onset of a pandemic. Our industry is known for its cyclical nature, so adapting to change is not a new concept. But dealing with the challenges posed by COVID-19 has been like nothing any of us have experienced before. QP Technologies has been fortunate to weather the pandemic well – less than 0.05% of our staff has tested positive, w... » read more

Chip Monitoring And Test Collaborate


As on-chip monitoring becomes more prevalent in complex advanced-node ICs, it’s easy to question whether or not it conflicts with conventional silicon testing. It might even supplant such testing in the future. Or alternatively, they could interact, with each supporting the other. “On-chip monitors provide fine-grained observability into effects and issues that are otherwise difficult or... » read more

The Darker Side Of Hybrid Bonding


With semiconductors, it's often things everyone takes for granted that cause the biggest headaches, and that problem is compounded when something fundamental changes — such as bonding two chips together using a process aimed at maximizing performance. Case in point: CMP for backend of the line metallization in hybrid bonding. While this is a mature process, it doesn't easily translate for ... » read more

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