Tech Talk: 7nm Litho


David Fried, chief technology officer at Coventor, digs into future scaling issues involving multi-patterning and new transistor types. https://youtu.be/FBnYRAL1xKY Related Stories Inside Next-Gen Transistors Coventor’s CTO looks at new types of transistors, the expanding number of challenges at future process nodes & the state of semiconductor development in China. Faster Time T... » read more

Inside FD-SOI And Scaling


Gary Patton, chief technology officer at [getentity id="22819" comment="GlobalFoundries"], sat down with Semiconductor Engineering to discuss FD-SOI, IC scaling, process technology and other topics. What follows are excerpts of that conversation. SE: In logic, GlobalFoundries is shipping 14nm finFETs with 7nm in the works. The company is also readying 22nm FD-SOI technology with 12nm FD-SOI ... » read more

Power Challenges At 10nm And Below


Current density is becoming much more problematic at 10nm and beyond, increasing the amount of power management that needs to be incorporated into each chip and boosting both design costs and time to market. Current per unit of area has been rising since 90nm, forcing design teams to leverage a number of power-related strategies such as [getkc id="143" kc_name="dynamic voltage and frequency... » read more

Inside Next-Gen Transistors


David Fried, chief technology officer at [getentity id="22210" e_name="Coventor"], sat down with Semiconductor Engineering to discuss the IC industry, China, scaling, transistors and process technology. What follows are excerpts of that conversation. SE: In a recent roundtable discussion you talked about some of the big challenges facing the IC industry. One of your big concerns involves th... » read more

What’s Next For Transistors


The IC industry is moving in several different directions at once. The largest chipmakers continue to march down process nodes with chip scaling, while others are moving towards various advanced packaging schemes. On top of that, post-CMOS devices, neuromorphic chips and quantum computing are all in the works. Semiconductor Engineering sat down to discuss these technologies with Marie Semeri... » read more

Transferring Skills Getting Harder


Rising complexity in developing chips at advanced nodes, and an almost perpetual barrage of new engineering challenges at each new node, are making it more difficult for everyone involved to maintain consistent skill levels across a growing number of interrelated technologies. The result is that engineers are being forced to specialize, but when they work with other engineers with different ... » read more

Uncertainty Grows For 5nm, 3nm


As several chipmakers ramp up their 10nm finFET processes, with 7nm just around the corner, R&D has begun for 5nm and beyond. In fact, some are already moving full speed ahead in the arena. [getentity id="22586" comment="TSMC"] recently announced plans to build a new fab in Taiwan at a cost of $15.7 billion. The proposed fab is targeted to manufacture TSMC’s 5nm and 3nm processes, whic... » read more

Pathfinding Beyond FinFETs


Though the industry will likely continue to find ways to extend CMOS finFET technology further than we thought possible, at some point in the not-so-distant future, making faster, lower power ICs will require more disruptive changes. For something that could be only five to seven years out, there’s a daunting range of contending technologies. Improvements through the process will help, from E... » read more

Pain Points At 7nm


Early work has begun on 7nm. Process technology has progressed to the point where IP and tools are being qualified. There is still a long way to go. But as companies begin engaging with foundries on this process node—[getentity id="22586" comment="TSMC"] is talking publicly about it, but [getentity id="22846" e_name="Intel"], [getentity id="22819" comment="GlobalFoundries"] and [getentity ... » read more

What’s After 10nm?


Prior to 28nm the semiconductor road map was astoundingly predictable. Every two years you could be assured that features would shrink until there were no more atoms left. Two big things and lots of little things later, the trajectory looks much more uncertain. On the large things side are the obvious culprits—EUV delays, and RC delay caused by thinner wires. This is tough science. Pro... » read more

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