tag: gate-all-around FETs

Backside Power Delivery Creates Fab Tool, Thermal Dissipation Barriers
By Laura Peters - 23 Feb, 2026 - Comments: 1

Key Takeaways Backside power delivery reduces routing congestion at the most advanced nodes and offers significant performance improvement options. But it also adds a bunch of new challenges involving via alignment and interconnects. Still, leading-edge foundries are making progress, and all of them plan to offer BPDNs at 2nm and below. Backside power delivery networks deliv... » read more

GAA NSFETs: ML for Device and Circuit Modeling
By Technical Paper Link - 30 Nov, 2023 - Comments: 0

A new technical paper titled "A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors" was published by researchers at National Yang Ming Chiao Tung University. Abstract (excerpt) "Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domai... » read more

Navigating the Metrology Maze For GAA FETs
By Gregory Haley - 08 Aug, 2023 - Comments: 1

The chip industry is pushing the boundaries of innovation with the evolution of finFETs to gate-all-around (GAA) nanosheet transistors at the 3nm node and beyond, but it also is adding significant new metrology challenges. GAA represents a significant advancement in transistor architecture, where the gate material fully encompasses the nanosheet channel. This approach allows for the vertical... » read more

Vertical Nanowire Gate-All-Around FETs based on the GeSn-Material System Grown on Si
By Technical Paper Link - 10 Apr, 2023 - Comments: 0

A new technical paper titled "Vertical GeSn nanowire MOSFETs for CMOS beyond silicon" was published by researchers at Peter Grünberg Institute 9, JARA, RWTH Aachen University, CEA, LETI, University of Grenoble Alpes, University of Leeds, and IHP. "Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transcon... » read more

Which Foundry Is In The Lead? It Depends.
By Ed Sperling - 26 Oct, 2022 - Comments: 2

The multi-billion-dollar race for foundry leadership is becoming more convoluted and complex, making it difficult to determine which company is in the lead at any time because there are so many factors that need to be weighed. This largely is a reflection of changes in the customer base at the leading edge and the push toward domain-specific designs. In the past, companies like Apple, Google... » read more

Who Benefits From Chiplets, And When
By Ed Sperling - 31 May, 2022 - Comments: 0

Experts at the Table: Semiconductor Engineering sat down to discuss new packaging approaches and integration issues with Anirudh Devgan, president and CEO of Cadence; Joseph Sawicki, executive vice president of Siemens EDA; Niels Faché, vice president and general manager at Keysight; Simon Segars, advisor at Arm; and Aki Fujimura, chairman and CEO of D2S. This discussion was held in front of a... » read more

Next-Gen Transistors
By Ed Sperling - 07 Mar, 2022 - Comments: 0

Nanosheets, or more generally, gate-all-around FETs, mark the next big shift in transistor structures at the most advanced nodes. David Fried, vice president of computational products at Lam Research, talks with Semiconductor Engineering about the advantages of using these new transistor types, along with myriad challenges at future nodes, particularly in the area of metrology. » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Wrestling With Analog At 3nm
By Brian Bailey - 09 Sep, 2021 - Comments: 0

Analog engineers are facing big challenges at 3nm, forcing them to come up with creative solutions to a widening set of issues at each new process node. Still, these problems must be addressed, because no digital chip will work without at least some analog circuitry. As fabrication technologies shrink, digital logic improves in some combination of power, performance, and area. The process te... » read more

Impact Of GAA Transistors At 3/2nm
By Brian Bailey - 16 Aug, 2021 - Comments: 2

The chip industry is poised for another change in transistor structure as gate-all-around (GAA) FETs replace finFETs at 3nm and below, creating a new set of challenges for design teams that will need to be fully understood and addressed. GAA FETs are considered an evolutionary step from finFETs, but the impact on design flows and tools is still expected to be significant. GAA FETs will offer... » read more

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