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On-Chip Power Distribution Modeling Becomes Essential Below 7nm


Modeling power distribution in SoCs is becoming increasingly important at each new node and in 3D-ICs, where tolerances involving power are much tighter and any mistake can cause functional failures. At mature nodes, where there is more metal, power problems continue to be rare. But at advanced nodes, where chips are running at higher frequencies and still consuming the same or greater power... » read more

High-Tech: Innovation At The Speed of Light


As connectivity, digitalization, and autonomy proliferate, the boundaries between industries are blurring at an unprecedented pace. Promising to unleash $3TN in global technology market spending, the new competitive battleground is to be found where the system electronics and semiconductor worlds collide: The 3D Integrated Circuit System-on-a-Chip. Winning demands a new design paradigm that ... » read more

Manufacturing Bits: Dec. 14


3D-SOCs At this week’s IEEE International Electron Devices Meeting (IEDM), a plethora of companies, R&D organizations and universities presented papers on the latest and greatest technologies. One of the themes at IEDM is advanced packaging, a technology enables an IC vendor to boost the performance of a chip. Advanced forms of packaging also enables new 3D-like chip architectures. Fo... » read more

What’s Next For Transistors And Chiplets


Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more