Why More CPUs Are Needed For Agentic AI


The shift from generative AI to agentic AI will significantly increase the amount of compute power needed in data centers. Queries to search for and analyze data from multiple sources will be performed simultaneously by agents and without human intervention, rather than a single request from a live person. Jeff Defilippi, senior director of product management at Arm, talks about the impact of r... » read more

Rethinking The Role Of CPUs In AI: A Practical RAG Implementation


In many enterprise environments, engineers and technical staff need to find information quickly. They search internal documents such as hardware specifications, project manuals, and technical notes. These materials are often scattered, making traditional search inefficient. These documents are often confidential or proprietary. This constraint prevents these documents from being processed by... » read more

The Rise Of AI Co-Processors


Figuring out the best kinds of processors to use for different AI workloads is a challenge. AI algorithms are undergoing rapid and frequent changes, and the workloads tied to them can vary by data type, by user, and sometimes because of software/firmware updates. On top of that, AI computations tend to require much higher utilization rates than traditional computing, and that will only become m... » read more

Data Center CPU Dominance Is Shifting To AMD And Arm


Fig. 1: Created by ChatGPT from a text prompt. The data center processor market has seen two major tectonic shifts in the last decade. It used to be that all data center compute was x86, and well more than 90% of that was Intel. GPUs first appeared in the data center in 2016 (Pascal GPU). Now, the majority of computation is done on GPUs. AMD is looking to pass Intel in x86 share, and... » read more

Striking A Balance On Efficiency, Performance, And Cost


Experts at the Table: Semiconductor Engineering sat down to discuss power-related issues such as voltage droop, application-specific processing elements, the impact of physical effects in advanced packaging, and the benefits of backside power delivery, with Hans Yeager, senior principal engineer, architecture, at Tenstorrent; Joe Davis, senior director for Calibre interfaces and EM/IR product m... » read more

Sensor Fusion Challenges In Automotive


The number of sensors in automobiles is growing rapidly alongside new safety features and increasing levels of autonomy. The challenge is integrating them in a way that makes sense, because these sensors are optimized for different types of data, sometimes with different resolution requirements even for the same type of data, and frequently with very different latency, power consumption, and re... » read more

LLM Inference On CPUs (Intel)


A technical paper titled “Efficient LLM Inference on CPUs” was published by researchers at Intel. Abstract: "Large language models (LLMs) have demonstrated remarkable performance and tremendous potential across a wide range of tasks. However, deploying these models has been challenging due to the astronomical amount of model parameters, which requires a demand for large memory capacity an... » read more

RISC-V Wants All Your Cores


RISC-V is no longer content to disrupt the CPU industry. It is waging war against every type of processor integrated into an SoC or advanced package, an ambitious plan that will face stiff competition from entrenched players with deep-pocketed R&D operations and their well-constructed ecosystems. When Calista Redmond, CEO for RISC-V International, said at last year's summit that RISC-V w... » read more

ISA and Microarchitecture Extensions Over Dense Matrix Engines to Support Flexible Structured Sparsity for CPUs (Georgia Tech, Intel Labs)


A technical paper titled "VEGETA: Vertically-Integrated Extensions for Sparse/Dense GEMM Tile Acceleration on CPUs" was published (preprint) by researchers at Georgia Tech and Intel Labs. Abstract: "Deep Learning (DL) acceleration support in CPUs has recently gained a lot of traction, with several companies (Arm, Intel, IBM) announcing products with specialized matrix engines accessible v... » read more

Dealing With Performance Bottlenecks In SoCs


A surge in the amount of data that SoCs need to process is bogging down performance, and while the processors themselves can handle that influx, memory and communication bandwidth are straining. The question now is what can be done about it. The gap between memory and CPU bandwidth — the so-called memory wall — is well documented and definitely not a new problem. But it has not gone away... » read more

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