tag: system-technology co-optimization

AI & Energy: Bending The Curve
By Pushkar Apte - 21 May, 2026 - Comments: 0

By Pushkar P. Apte and Melissa Grupen-Shemansky Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits, but the growth comes with an escalating demand for power, and energy has emerged as a major challenge. The AI & energy challenge AI training c... » read more

Opening The Door To STCO: Hierarchical Device Planning
By Todd Burkholder - 29 Jan, 2026 - Comments: 0

By Todd Burkholder and Per Viklund The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance market segments, such as AI, hyperscalers, high-performance computing, cloud data centers, neural processors, and even autonomous vehicles. This increased design complexity has led to an explosion in device complexity and pin counts. It... » read more

The Need for System-Technology Co-Optimization (STCO)
By Benjamin Prautsch - 11 Sep, 2025 - Comments: 0

Modern semiconductor components are becoming more and more complex and cost sensitive. To master technological and economic challenges, new chiplet approaches and heterogeneous integration technologies are becoming increasingly relevant. This, in turn, calls for new heterogeneous design approaches. They make it possible to combine different design domains across technological options while sati... » read more

Industry Leaders Provide Insights And Guidance On Multi-Die Designs
By Frank Malloy - 12 Jun, 2025 - Comments: 0

Multi-die designs seamlessly integrate multiple heterogeneous or homogeneous dies in a single package to significantly enhance chip performance and efficiency — making them indispensable for high-performance computing (HPC), artificial intelligence (AI), data analytics, advanced graphics processing, and other demanding applications. While representing a groundbreaking leap forward, multi-d... » read more

Inside Chips Podcast: May 27
By Gregory Haley - 27 May, 2025 - Comments: 0

Jo De Boeck, chief strategy officer and EVP at imec, talks with Semiconductor Engineering Technology Editor Gregory Haley about system technology co-optimization and the intersection of technology and AI. https://www.youtube.com/watch?v=XUgQPBIaDHQ » read more

IEDM Keynote: Ann Kelleher On Future Technology
By Paul McLellan - 21 Dec, 2022 - Comments: 0

IEDM 2022 celebrated 75 Years of the Transistor. I can't imagine anything else invented in the last 75 years has had as much effect on my life, and probably yours, too. After the awards session, the conference got underway with a keynote by Ann Kelleher, Executive Vice President and General Manager of Technology Development at Intel. It was titled "Celebrating 75 Years of the Transistor! A L... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Architecting Interposers
By Brian Bailey - 14 Oct, 2021 - Comments: 0

An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

Shifting Left: Early Multi Physics Analysis For STCO
By Per Viklund - 24 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously desi... » read more

Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration
By Siemens EDA - 23 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchrono... » read more

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