tag: system-technology co-optimization

IEDM Keynote: Ann Kelleher On Future Technology
By Paul McLellan - 21 Dec, 2022 - Comments: 0

IEDM 2022 celebrated 75 Years of the Transistor. I can't imagine anything else invented in the last 75 years has had as much effect on my life, and probably yours, too. After the awards session, the conference got underway with a keynote by Ann Kelleher, Executive Vice President and General Manager of Technology Development at Intel. It was titled "Celebrating 75 Years of the Transistor! A L... » read more

What’s Next For Transistors And Chiplets
By Mark LaPedus - 21 Oct, 2021 - Comments: 5

Sri Samavedam, senior vice president of CMOS Technologies at Imec, sat down with Semiconductor Engineering to talk about finFET scaling, gate-all-around transistors, interconnects, packaging, chiplets and 3D SoCs. What follows are excerpts of that discussion. SE: The semiconductor technology roadmap is moving in several different directions. We have traditional logic scaling, but packaging i... » read more

Architecting Interposers
By Brian Bailey - 14 Oct, 2021 - Comments: 0

An interposer performs a similar function as a printed circuit board (PCB), but when the interposer is moved inside a package the impact is significant. Neither legacy PCB nor IC design tools can fully perform the necessary design and analysis tasks. But perhaps even more important, adding an interposer to a design may require organizational changes. Today, leading-edge companies have shown ... » read more

Shifting Left: Early Multi Physics Analysis For STCO
By Per Viklund - 24 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the emergence of a system technology co-optimization (STCO) approach, in which an SoC is disaggregated into smaller modules (also known as chiplets) that can be asynchronously desi... » read more

Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration
By Siemens EDA - 23 Jun, 2021 - Comments: 0

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchrono... » read more

Extending The IC Roadmap
By Mark LaPedus - 11 Jun, 2018 - Comments: 0

An Steegen, executive vice president of semiconductor technology and systems at Imec, sat down with Semiconductor Engineering to discuss IC scaling and chip packaging. Imec is working on next-generation transistors, but it is also developing several new technologies for IC packaging, such as a proprietary silicon bridge, a cooling technology and packaging modules. What follows are excerpts of t... » read more

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2024 SMG   |  Terms of Service  |  Privacy Policy