Opening The Door To STCO: Hierarchical Device Planning

By Todd Burkholder and Per Viklund

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance market segments, such as AI, hyperscalers, high-performance computing, cloud data centers, neural processors, and even autonomous vehicles.

This increased design complexity has led to an explosion in device complexity and pin counts. It also requires the use of a system-level design approach that leverages iterative multi-physics analysis during the floorplanning stage and supports optimization of the chiplets, the interposers, and the package substrate to achieve PPA and cost goals—significantly lowering the barrier for project success.

Fig. 1: 3D IC increases the flexibility and challenges of electronic system design.

Package pin counts have surged from approximately 100,000 or fewer pins just a few years ago to upwards of 50 million pins in contemporary designs. Projections indicate a potential tenfold increase in these numbers within the next few years, creating a profound impact across every facet of the semiconductor ecosystem.

A solution capable of abstracting this intricate complexity into manageable portions is not merely advantageous; it is indispensable. Hierarchical device planning (HDP) emerges as a critical methodology specifically engineered to decompose overwhelming design challenges into digestible, manageable segments, offering a strategic pathway through this complex landscape. As such, HDP with smart pin regions enables a more robust and flexible level of System Technology Co-Optimization (STCO).

This article advocates a process where IC partitioning information is forwarded to package prototyping at an early stage, allowing for an immediate analysis of physical effects. Hierarchical device planning directly addresses this by integrating established hierarchical design methodology techniques into the realm of advanced IC packaging and, as such, enables more robust and flexible STCO.

Solutions derived from this package prototyping, guided by multi-physics analysis, are then communicated back to the silicon teams. This feedback loop helps drive IP partitioning and empowers IC design teams to make more informed decisions at a stage where partitioning can still be modified, before the design progresses too far and the costs of rectifying problems become prohibitive.

Hierarchical device planning directly addresses this by integrating established hierarchical design methodology techniques—long characteristic of chip design—into the realm of advanced IC packaging. This approach is crucial for managing the intricate interface connectivity inherent in package devices composed of numerous smaller building blocks.

STCO is the key to 3D-IC

With the economic advantages of transistor scaling no longer universally applicable, the semiconductor industry is increasingly embracing innovative packaging technologies to meet system scaling demands and achieve lower overall system costs. This strategic pivot has led to the emergence of STCO, an approach where a monolithic system-on-chip (SoC) is disaggregated into smaller functional modules, or chiplets. These chiplets can then be designed asynchronously by different teams and subsequently integrated into a larger, highly flexible system using advanced package technologies.

Fig. 2: Arrayed blocks are used to construct a chiplet.

Early system partitioning and integration planning exert a profound influence on physical implementation across various critical domains, including power integrity, signal integrity, thermal performance, package warping, and mechanical stress. Inadequate management of these aspects during the initial design phases can lead to catastrophic product failure. During the early partitioning process, the physical ramifications of a chosen partitioning option are not immediately apparent, but while detailed simulations are not yet feasible due to a lack of granular design information, rapid, approximate analyses can provide crucial insights, helping to identify potential issues before they become deeply embedded in the design.

STCO offers numerous benefits, including the ability for design teams to work concurrently yet asynchronously, leveraging optimal processes for each design fragment. However, this distributed approach also introduces challenges. The data from all these disparate fragments must ultimately converge during the package planning phase, where the disaggregated SoC functional blocks are reassembled, and packaging options are evaluated. The manner in which the design is partitioned directly impacts the feasibility and cost of the final package. It is often the case that silicon design teams, lacking downstream insight or the means to assess the packaging implications of their decisions, make partitioning choices that inadvertently complicate package integration.

The primary challenge, then, lies in effectively reintegrating these design fragments into an early package prototype. This prototype must contain sufficient information to facilitate multi-physics analysis, thereby guiding the partitioning process. Such analysis yields critical information, which, when fed back to the silicon design teams, empowers them to make informed decisions and reconsider partitioning choices if necessary, all while the cost of change remains relatively low.

HDP is the key to STCO

A cornerstone of effective STCO is the ability to conduct multi-domain analyses—for example, signal integrity, power integrity, thermal performance, and mechanical stress—at a very early stage in the design cycle. To achieve this, designers must be able to rapidly create package bump maps and precisely place chiplets within the 3D space.

Fig. 3: Connectivity in a hierarchical IC package floorplan, showing that bumps within the sub-devices are represented at the top level.

Hierarchical device planning provides the capability to quickly generate a prototype package configuration, enabling immediate analysis to guide design decisions. This early analysis often uncovers issues that, if discovered at the traditional post-layout stage, would necessitate a complete and exceedingly costly redesign. With HDP, these issues are identified early, allowing corrective actions to be taken when the cost of change is minimal—a fundamental principle of a “shift-left” strategy.

Beyond its hierarchical nature, HDP offers a key advantage through its parametric capabilities. This parameterization allows designers to rapidly redefine bump arrays to address issues identified during simulation. For example, parameters such as bump pitch, pattern, shape, or size, or even the assignment of bumps to power and ground nets, can be modified. By simply adjusting parameters for one or more bump array regions, the design automatically updates, preparing it for the next simulation run. This iterative process, which previously could consume days or weeks, now takes mere seconds. This efficiency enables designers to quickly prototype packages, run analyses, implement design changes, and re-simulate in a continuous loop until optimal results are achieved.

Fig. 4: A design of arrayed HDP blocks created with parameterized pin regions.

It is important to clarify that for early predictive analysis, the absolute accuracy percentage of the simulation is not the paramount concern. Rather, the analysis needs to be sufficiently accurate to guide the designer in selecting the most appropriate approach from several viable alternatives. This early guidance facilitates STCO at a stage where significant design modifications can be implemented at a minimal cost. HDP is thus critical in enabling this agile design flow.

A significant challenge in advanced packaging involves optimizing smaller functional areas within a package and subsequently reusing these optimized blocks in derivative designs. HDP directly addresses this by integrating established hierarchical design methodology techniques—long a hallmark of chip design—into the realm of advanced IC packaging. This approach is crucial for managing the intricate interface connectivity inherent in package devices composed of numerous smaller building blocks. However, before fully adopting a hierarchical design implementation strategy, it is essential to acknowledge the unique challenges of IC packaging, particularly that at the top-level hierarchical floorplans often require a distinct set of signals for each instance of a placed building block.

It is crucial to remember that a package now comprises multiple designs that are heterogeneously integrated together to function better than the sum of their parts, including chiplets, interposers, silicon bridges, and other elements. Relying on traditional, disconnected methods for such complex assemblies introduces an unacceptably high risk of failure, mandating a transition to a more synchronized and integrated design methodology. This is precisely where HDP introduces a new paradigm and underscores the need for robust, error-preventing methodologies and tools from the outset. HDP’s core innovation lies in the ability to hierarchically define parameterized regions of component pins. Instead of grappling with the minutiae of every single pin and its connectivity, designers can now work with these abstracted, hierarchically defined regions. This allows them to plan, design, analyze, and optimize the overall package layout at a higher level of abstraction, deferring the detailed pin-level considerations until they are genuinely necessary.

A significant advantage of this approach is the automatic synthesis of all pins according to the parameters set within these defined regions. Package designers are intimately familiar with the frequent design changes that occur throughout the development flow. With hierarchical device planning, designers can simply modify the relevant parameters of a region, and the system automatically updates the circuit. This capability can save days, or even weeks, of design effort, representing a critical leap in efficiency and responsiveness to design iterations.

Managing HDP and STCO

Chiplets offer a modular solution, providing smaller, convenient building blocks that communicate via standardized interfaces, thereby enabling more flexible and cost-effective system integration. With targeted, advanced tools and methodologies, designers can more effectively tackle the complexities of 3D ICs and heterogeneous integration, ensuring the successful realization of next-generation electronic systems. Siemens’ Innovator3D IC portfolio solution exemplifies this integrated approach, supporting designers from initial planning and optimization through detailed analysis and package layout.

Fig. 5: Innovator3D IC solution suite cockpit.

A critical component of this solution is robust work-in-progress data management. The sheer volume of data involved in a modern package design demands meticulous tracking to ensure the correct versions of all files are utilized. Forgetting to import an updated Verilog file, for instance, can lead to the fabrication of an incorrect package. Automated tracking and error detection mechanisms are vital to mitigate the numerous potential points of failure. By integrating these capabilities within a unified, AI-infused user experience, solutions like the Innovator 3D IC solution suite are intuitive and efficient for designers to adopt and utilize.

Early system partitioning and integration planning profoundly impact physical implementation across critical domains, such as power integrity, signal integrity, thermal performance, package warping, and mechanical stress. If these aspects are not managed effectively, they can lead to complete product failure. During the initial partitioning process, the physical consequences of various options are not immediately visible. Even when detailed simulations are not yet possible, rapid approximate analyses can provide crucial insights, helping to identify potential issues early.

By actively seeking out and adopting new advanced tools and methodologies that support STCO, HDP, and 3D IC standards, designers can more effectively tackle the complexities of 3D ICs and heterogeneous integration, ensuring the successful realization of next-generation electronic systems. In essence, this approach enables earlier, more strategic decision-making, embodying the shift-left philosophy that will help teams realize tomorrow’s innovations today.

For more in depth look at these two technologies, please read the new paper from Siemens, Hierarchical device planning: Navigating 3D IC intricacies with STCO.

Per Viklund is Systems Architect Director at Siemens EDA responsible for IC Packaging and RF/Microwave technologies. He has more than 40 years’ experience with electronic design and EDA and has spent the last 30 years in EDA focusing on High Density Advanced Packaging (HDAP) and RF/microwave design. He has published multiple papers on RF, IC Packaging and Package Co-design.