tag: STCO

AI & Energy: Bending The Curve
By Pushkar Apte - 21 May, 2026 - Comments: 0

By Pushkar P. Apte and Melissa Grupen-Shemansky Artificial intelligence (AI) is scaling at a pace that is reshaping semiconductor roadmaps, data center design, and long-term infrastructure strategy. AI promises many economic and social benefits, but the growth comes with an escalating demand for power, and energy has emerged as a major challenge. The AI & energy challenge AI training c... » read more

Beating The Heat In 3D Packages
By Laura Peters - 25 Mar, 2026 - Comments: 0

Key Takeaways: Thermal management is a central design constraint, requiring early, thorough planning. Accurate thermal simulation requires AI-driven adaptive meshing and real-world validation. Innovative STCO strategies can drastically reduce GPU peak temperature. As HPC and AI accelerators push power densities to 1kW and beyond, the heat generated by rapidly switching tran... » read more

Opening The Door To STCO: Hierarchical Device Planning
By Todd Burkholder - 29 Jan, 2026 - Comments: 0

By Todd Burkholder and Per Viklund The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance market segments, such as AI, hyperscalers, high-performance computing, cloud data centers, neural processors, and even autonomous vehicles. This increased design complexity has led to an explosion in device complexity and pin counts. It... » read more

The Need for System-Technology Co-Optimization (STCO)
By Benjamin Prautsch - 11 Sep, 2025 - Comments: 0

Modern semiconductor components are becoming more and more complex and cost sensitive. To master technological and economic challenges, new chiplet approaches and heterogeneous integration technologies are becoming increasingly relevant. This, in turn, calls for new heterogeneous design approaches. They make it possible to combine different design domains across technological options while sati... » read more

Industry Leaders Provide Insights And Guidance On Multi-Die Designs
By Frank Malloy - 12 Jun, 2025 - Comments: 0

Multi-die designs seamlessly integrate multiple heterogeneous or homogeneous dies in a single package to significantly enhance chip performance and efficiency — making them indispensable for high-performance computing (HPC), artificial intelligence (AI), data analytics, advanced graphics processing, and other demanding applications. While representing a groundbreaking leap forward, multi-d... » read more

TCAD For GPUs And GPUs For TCAD
By Shela Aboud - 17 Apr, 2025 - Comments: 0

It is well known that many steps in chip development become exponentially harder as feature sizes shrink and instance counts balloon. Billions of transistors are now commonplace, and wafer-scale devices with trillions are on the horizon. Such massive chips put pressure on every electronic design automation (EDA) tool in the development flow, from front-end architectural modeling to signoff and ... » read more

STCO for Dense Edge Architectures using 3D Integration and NVM (imec,, et al.)
By Technical Paper Link - 27 Nov, 2024 - Comments: 0

A new technical paper titled "System-Technology Co-Optimization for Dense Edge Architectures using 3D Integration and Non-Volatile Memory" was published by researchers at imec, INESC-ID, Université Libre de Bruxelles, et al. "In this paper, we present an system-technology co-optimization (STCO) framework that interfaces with workload-driven system scaling challenges and physical design-enab... » read more

DTCO/STCO Create Path For Faster Yield Ramps
By Laura Peters - 12 Mar, 2024 - Comments: 0

Higher density in planar SoCs and advanced packages, coupled with more complex interactions and dependencies between various components, are permitting systematic defects to escape traditional detection methods. These issues increasingly are not detected until the chips reach high-volume manufacturing, slowing the yield ramp and bumping up costs. To combat these problems, IDMs and systems co... » read more

Everyone’s A System Designer With Heterogeneous Integration
By Ann Mutschler - 02 Oct, 2023 - Comments: 0

The move away from monolithic SoCs to heterogeneous chips and chiplets in a package is accelerating, setting in motion a broad shift in methodologies, collaborations, and design goals that are felt by engineers at every step of the flow, from design through manufacturing. Nearly every engineer is now working or touching some technology, process, or methodology that is new. And they are inter... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

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