IEDM Keynote: Ann Kelleher On Future Technology

System technology co-optimization and Intel’s roadmap.


IEDM 2022 celebrated 75 Years of the Transistor. I can’t imagine anything else invented in the last 75 years has had as much effect on my life, and probably yours, too.

After the awards session, the conference got underway with a keynote by Ann Kelleher, Executive Vice President and General Manager of Technology Development at Intel. It was titled “Celebrating 75 Years of the Transistor! A Look Ahead Towards the Next Generation of Innovation Opportunities.”

I think Ann has one of the most challenging jobs in the entire semiconductor industry, illustrated by one slide that she presented near the end of her presentation:

You probably know that Intel was late with what it used to call 10nm and now calls Intel 7. It is now in high-volume manufacturing (HVM) and is pumping out Alder Lake, Raptor Lake, and Sapphire Rapids.

The next generation process is Intel 4, which used to be called 7nm. It is “manufacturing ready.” I’m not quite sure precisely what that means. It either is being used, or will be, to manufacture Meteor Lake. As I wrote in my post HOT CHIPS Day 2: AI…and More Hot Chiplets, Meteor Lake is a 3D heterogeneous integration design:

This has a CPU tile, a GPU tile, an SoC tile, an I/O extender tile, and underneath it all, a base tile. Meteor Lake has been booted in the lab.

I think just the CPU and GPU tiles are built in Intel 4.

Intel 3 should be ready in the second half of next year.

The next process is Intel 20A (the A stands for Ångström), which is planned for the first half of 2024 (to be used for Arrow Lake). This is a ribbon-FET (gate-all-around) process.

Then Intel 18A is meant to be ready in the second half of 2024 (perhaps the process for Lunar Lake). This process is one that will be available to foundry customers. This node is planned to be the first to use High-NA EUV if ASML can get it to work by then (see my post What Is High-NA EUV?).

That’s five process generations in three or four years (depending on where you start counting). I don’t think any company has ever attempted to do anything so ambitious. Of course, the next few years will tell whether Intel succeeds at doing this and “leapfrogging” the competition. Some of this may just be naming. Intel 18A may be an optical shrink of Intel 20A, rather than a true process node.

Ann’s Keynote

Ann opened with her key messages:

  • Moore’s Law is about innovation and is vital to addressing computing demand. Okay, that’s a bit “motherhood and apple pie.”
  • System-based technology co-optimization (STCO) is the next major evolution of innovation. This was presented as something brand new, but it turns out my first mention of STCO was in June 2018 in my post Imec Roadmap.
  • Challenges and opportunities are plentiful and require continued innovation across the entire ecosystem. This is what she spent a lot of her presentation covering.

As I said above, one of her top-level points is that the future belongs to STCO. Among other things, this means implementing systems using chiplets (which Intel usually calls “tiles”) and using Design Technology Co-Optimization to optimize the design-process interface (things like backside power distribution or via pillars). Of course, there is a flow to integrate the entire system, design the package, and manufacture it. Intel has two 3D packaging technologies called Foveros and EMIB, and they come in different flavors. Foveros Direct is a direct copper-to-copper assembly approach.

STCO for a system starts right at the top with applications and workloads, and the software load. This drives the system architecture at a high level, basically how to partition the design into chiplets. Within the chiplets, there is foundational IP (standard cells, memories) but also core and accelerator IP (for foundry, Intel supports x86, Arm, and RISC-V). Right at the bottom is Ann’s domain: transistors and interconnects, and the semiconductor processes used to manufacture them.

The middle part of Ann’s presentation was digging into various areas and looking at opportunities for the future. There is much too much to cover in a blog post, so I’ll just list the topic areas:

  • People
  • Transistors
  • Interconnect
  • Materials
  • Reliability
  • Memory
  • Patterning
  • Software
  • Disaggregation
  • Manufacturing
  • Advanced packaging

After covering the status of the process roadmap (which I opened this post with), Ann wrapped up with a glimpse of what research areas Intel is working on:

  • An additional 10X improvement in density and placement flexibility for chiplet-based designs.
  • Super thin materials to allow scaling to continue (using 2D materials for transistors once RibbonFET (GAA) runs out of steam).
  • New possibilities in energy efficiency (GaN on silicon) and memory (FeRAM magneto-electric devices).

Her last slide was how Intel considers itself to be the “steward of Moore’s Law”. Of course, Gordon Moore was one of the founders of Intel, and its CEO from 1979 to 1987. Intel’s aspiration is for 1 trillion transistor designs by 2030.

IEEE Spectrum interviewed Ann (I presume before she had given the keynote) and published its piece Intel’s Take on the Next Wave of Moore’s Law.

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