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Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration

Working with dispersed teams to create a highly flexible chiplet-based design.

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With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchronously designed by dispersed teams and then combined into a larger, highly flexible system using chiplet-based package design, which may involve 3D packaging.

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