Partitioning Processors For AI Workloads

Partitioning in complex chips is beginning to resemble a high-stakes guessing game, where choices need to extrapolate from what is known today to what is expected by the time a chip finally ships. Partitioning of workloads used to be a straightforward task, although not necessarily a simple one. It depended on how a device was expected to be used, the various compute, storage and data paths ... » read more

True 3D Is Much Tougher Than 2.5D

Creating real 3D designs is proving to be much more complex and difficult than 2.5D, requiring significant innovation in both technology and tools. While there has been much discussion about 3D designs, there are multiple interpretations about what 3D entails. This is more than just semantics, however, because each packaging option requires different design approaches and technologies. And a... » read more

Costs of Static HW Partitioning on RISC-V

A new technical paper titled "Static Hardware Partitioning on RISC-V -- Shortcomings, Limitations, and Prospects" was published by researchers at Technical University of Applied Sciences (Regensburg, Germany) and Siemens AG (Corporate Research). Abstract "On embedded processors that are increasingly equipped with multiple CPU cores, static hardware partitioning is an established means of c... » read more

Structural Vs. Functional

When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Partitioning For Better Performance And Power

Partitioning is becoming more critical and much more complex as design teams balance different ways to optimize performance and power, shifting their focus from a single chip to a package or system involving multiple chips with very specific tasks. Approaches to design partitioning have changed over the years, most recently because processor clock speeds have hit a wall while the amount of d... » read more

Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration

With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchrono... » read more

Shifting Auto Architectures

Domain controllers and gateways are being replaced by central processing modules and zonal gateways to handle all of the data traffic in a vehicle. Ron DiGiuseppe, automotive IP segment manager at Synopsys, talks with Semiconductor Engineering about how automotive applications are changing, what that means for engineering teams, and how they will shift as AI is increasingly deployed. » read more

Design Issues For Chips Over Longer Lifetimes

Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

Is Hardware-Assisted Verification Avoidable?

Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Challenges At 3/2nm

David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

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