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Structural Vs. Functional


When working on an article about PLM and semiconductors, I got to review a favorite topic from my days in EDA development – verification versus validation. I built extensive presentations around it and tried to persuade people within the EDA industry, as well as customers, about the advantages of doing a top-down functional modeling and analysis. The V diagram that everyone uses is flawed and... » read more

Partitioning For Better Performance And Power


Partitioning is becoming more critical and much more complex as design teams balance different ways to optimize performance and power, shifting their focus from a single chip to a package or system involving multiple chips with very specific tasks. Approaches to design partitioning have changed over the years, most recently because processor clock speeds have hit a wall while the amount of d... » read more

Using A System Technology Co-Optimization (STCO) Approach For 2.5/3D Heterogeneous Semiconductor Integration


With the economics of transistor scaling no longer universally applicable, the industry is turning to innovative packaging technologies to support system scaling demands and achieve lower system cost. This has led to the system technology co-optimization (STCO) concept, where a SoC type system is disaggregated, or partitioned, into smaller modules (also known as chiplets) that can be asynchrono... » read more

Shifting Auto Architectures


Domain controllers and gateways are being replaced by central processing modules and zonal gateways to handle all of the data traffic in a vehicle. Ron DiGiuseppe, automotive IP segment manager at Synopsys, talks with Semiconductor Engineering about how automotive applications are changing, what that means for engineering teams, and how they will shift as AI is increasingly deployed. » read more

Design Issues For Chips Over Longer Lifetimes


Semiconductor Engineering sat down to discuss the myriad challenges associated with chips used in complex systems over longer periods of time them with Jean-Marie Brunet, senior director for the Emulation Division at Siemens EDA; Frank Schirrmeister, senior group director for solution marketing at Cadence; Maurizio Griva, R&D Manager at Reply; and Laurent Maillet-Contoz, system and architec... » read more

Is Hardware-Assisted Verification Avoidable?


Emulation is emerging as the tool of choice for complex and large designs, but companies that swap from simulation to emulation increasingly recognize this is not an easy transition. It requires money, time, and effort, and even then not everyone gets it right. Still, there are significant benefits to moving from simulation to emulation, providing these systems can be utilized efficiently en... » read more

Challenges At 3/2nm


David Fried, vice president of computational products at Lam Research, talks about issues at upcoming process nodes, the move to EUV lithography and nanosheet transistors, and how process variation can affect yield and device performance. » read more

Making Everything Linux-Capable


It's not clear how the edge will play out or what will be the winning formula from a hardware standpoint. But for everything beyond the end device, and possibly even including the end device, a key prerequisite will be the ability to run Linux. That means at least one processor or core within the hardware will need to run 64-bit software. In addition, systems will need to have enough storage... » read more

Getting Particular About Partitioning


Partitioning could well be one of the most important and pervasive trends since the invention of computers. It has been around for almost as long, too. The idea dates back at least as far back as the Manhattan Project during World War II, when computations were wrapped within computations. It continued from there with what we know as time-sharing, which rather crudely partitioned access by p... » read more

New Architectures, Much Faster Chips


The chip industry is making progress in multiple physical dimensions and with multiple architectural approaches, setting the stage for huge performance increases based on more modular and heterogeneous designs, new advanced packaging options, and continued scaling of digital logic for at least a couple more process nodes. A number of these changes have been discussed in recent conferences. I... » read more

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